Diff markup
1 /* 1 /*
2 * Promise PATA TX2/TX4/TX2000/133 IDE driver 2 * Promise PATA TX2/TX4/TX2000/133 IDE driver for pdc20268 to pdc20277.
3 * 3 *
4 * This program is free software; you can red 4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU Gener 5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundati 6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any 7 * 2 of the License, or (at your option) any later version.
8 * 8 *
9 * Ported to libata by: 9 * Ported to libata by:
10 * Albert Lee <albertcc@tw.ibm.com> IBM Corpo 10 * Albert Lee <albertcc@tw.ibm.com> IBM Corporation
11 * 11 *
12 * Copyright (C) 1998-2002 Andre 12 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
13 * Portions Copyright (C) 1999 Promise Techno 13 * Portions Copyright (C) 1999 Promise Technology, Inc.
14 * 14 *
15 * Author: Frank Tiernan (frankt@promise.com) 15 * Author: Frank Tiernan (frankt@promise.com)
16 * Released under terms of General Public Lic 16 * Released under terms of General Public License
17 * 17 *
18 * 18 *
19 * libata documentation is available via 'mak 19 * libata documentation is available via 'make {ps|pdf}docs',
20 * as Documentation/DocBook/libata.* 20 * as Documentation/DocBook/libata.*
21 * 21 *
22 * Hardware information only available under 22 * Hardware information only available under NDA.
23 * 23 *
24 */ 24 */
25 #include <linux/kernel.h> 25 #include <linux/kernel.h>
26 #include <linux/module.h> 26 #include <linux/module.h>
27 #include <linux/pci.h> 27 #include <linux/pci.h>
28 #include <linux/init.h> 28 #include <linux/init.h>
29 #include <linux/blkdev.h> 29 #include <linux/blkdev.h>
30 #include <linux/delay.h> 30 #include <linux/delay.h>
31 #include <linux/device.h> 31 #include <linux/device.h>
32 #include <scsi/scsi.h> 32 #include <scsi/scsi.h>
33 #include <scsi/scsi_host.h> 33 #include <scsi/scsi_host.h>
34 #include <scsi/scsi_cmnd.h> 34 #include <scsi/scsi_cmnd.h>
35 #include <linux/libata.h> 35 #include <linux/libata.h>
36 36
37 #define DRV_NAME "pata_pdc2027x" 37 #define DRV_NAME "pata_pdc2027x"
38 #define DRV_VERSION "1.0" 38 #define DRV_VERSION "1.0"
39 #undef PDC_DEBUG 39 #undef PDC_DEBUG
40 40
41 #ifdef PDC_DEBUG 41 #ifdef PDC_DEBUG
42 #define PDPRINTK(fmt, args...) printk(KERN_ERR 42 #define PDPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args)
43 #else 43 #else
44 #define PDPRINTK(fmt, args...) 44 #define PDPRINTK(fmt, args...)
45 #endif 45 #endif
46 46
47 enum { 47 enum {
48 PDC_MMIO_BAR = 5, 48 PDC_MMIO_BAR = 5,
49 49
50 PDC_UDMA_100 = 0, 50 PDC_UDMA_100 = 0,
51 PDC_UDMA_133 = 1, 51 PDC_UDMA_133 = 1,
52 52
53 PDC_100_MHZ = 100000000, 53 PDC_100_MHZ = 100000000,
54 PDC_133_MHZ = 133333333, 54 PDC_133_MHZ = 133333333,
55 55
56 PDC_SYS_CTL = 0x1100, 56 PDC_SYS_CTL = 0x1100,
57 PDC_ATA_CTL = 0x1104, 57 PDC_ATA_CTL = 0x1104,
58 PDC_GLOBAL_CTL = 0x1108, 58 PDC_GLOBAL_CTL = 0x1108,
59 PDC_CTCR0 = 0x110C, 59 PDC_CTCR0 = 0x110C,
60 PDC_CTCR1 = 0x1110, 60 PDC_CTCR1 = 0x1110,
61 PDC_BYTE_COUNT = 0x1120, 61 PDC_BYTE_COUNT = 0x1120,
62 PDC_PLL_CTL = 0x1202, 62 PDC_PLL_CTL = 0x1202,
63 }; 63 };
64 64
65 static int pdc2027x_init_one(struct pci_dev *p 65 static int pdc2027x_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
66 static int pdc2027x_prereset(struct ata_link * !! 66 static void pdc2027x_error_handler(struct ata_port *ap);
67 static void pdc2027x_set_piomode(struct ata_po 67 static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev);
68 static void pdc2027x_set_dmamode(struct ata_po 68 static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev);
69 static int pdc2027x_check_atapi_dma(struct ata 69 static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc);
70 static unsigned long pdc2027x_mode_filter(stru 70 static unsigned long pdc2027x_mode_filter(struct ata_device *adev, unsigned long mask);
71 static int pdc2027x_cable_detect(struct ata_po 71 static int pdc2027x_cable_detect(struct ata_port *ap);
72 static int pdc2027x_set_mode(struct ata_link * 72 static int pdc2027x_set_mode(struct ata_link *link, struct ata_device **r_failed);
73 73
74 /* 74 /*
75 * ATA Timing Tables based on 133MHz controlle 75 * ATA Timing Tables based on 133MHz controller clock.
76 * These tables are only used when the control 76 * These tables are only used when the controller is in 133MHz clock.
77 * If the controller is in 100MHz clock, the A 77 * If the controller is in 100MHz clock, the ASIC hardware will
78 * set the timing registers automatically when 78 * set the timing registers automatically when "set feature" command
79 * is issued to the device. However, if the co 79 * is issued to the device. However, if the controller clock is 133MHz,
80 * the following tables must be used. 80 * the following tables must be used.
81 */ 81 */
82 static struct pdc2027x_pio_timing { 82 static struct pdc2027x_pio_timing {
83 u8 value0, value1, value2; 83 u8 value0, value1, value2;
84 } pdc2027x_pio_timing_tbl [] = { 84 } pdc2027x_pio_timing_tbl [] = {
85 { 0xfb, 0x2b, 0xac }, /* PIO mode 0 */ 85 { 0xfb, 0x2b, 0xac }, /* PIO mode 0 */
86 { 0x46, 0x29, 0xa4 }, /* PIO mode 1 */ 86 { 0x46, 0x29, 0xa4 }, /* PIO mode 1 */
87 { 0x23, 0x26, 0x64 }, /* PIO mode 2 */ 87 { 0x23, 0x26, 0x64 }, /* PIO mode 2 */
88 { 0x27, 0x0d, 0x35 }, /* PIO mode 3, I 88 { 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */
89 { 0x23, 0x09, 0x25 }, /* PIO mode 4, I 89 { 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */
90 }; 90 };
91 91
92 static struct pdc2027x_mdma_timing { 92 static struct pdc2027x_mdma_timing {
93 u8 value0, value1; 93 u8 value0, value1;
94 } pdc2027x_mdma_timing_tbl [] = { 94 } pdc2027x_mdma_timing_tbl [] = {
95 { 0xdf, 0x5f }, /* MDMA mode 0 */ 95 { 0xdf, 0x5f }, /* MDMA mode 0 */
96 { 0x6b, 0x27 }, /* MDMA mode 1 */ 96 { 0x6b, 0x27 }, /* MDMA mode 1 */
97 { 0x69, 0x25 }, /* MDMA mode 2 */ 97 { 0x69, 0x25 }, /* MDMA mode 2 */
98 }; 98 };
99 99
100 static struct pdc2027x_udma_timing { 100 static struct pdc2027x_udma_timing {
101 u8 value0, value1, value2; 101 u8 value0, value1, value2;
102 } pdc2027x_udma_timing_tbl [] = { 102 } pdc2027x_udma_timing_tbl [] = {
103 { 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 * 103 { 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */
104 { 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 * 104 { 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */
105 { 0x2a, 0x07, 0xcd }, /* UDMA mode 2 * 105 { 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */
106 { 0x1a, 0x05, 0xcd }, /* UDMA mode 3 * 106 { 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */
107 { 0x1a, 0x03, 0xcd }, /* UDMA mode 4 * 107 { 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */
108 { 0x1a, 0x02, 0xcb }, /* UDMA mode 5 * 108 { 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */
109 { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 * 109 { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */
110 }; 110 };
111 111
112 static const struct pci_device_id pdc2027x_pci 112 static const struct pci_device_id pdc2027x_pci_tbl[] = {
113 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_P 113 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20268), PDC_UDMA_100 },
114 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_P 114 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20269), PDC_UDMA_133 },
115 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_P 115 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20270), PDC_UDMA_100 },
116 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_P 116 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20271), PDC_UDMA_133 },
117 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_P 117 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20275), PDC_UDMA_133 },
118 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_P 118 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20276), PDC_UDMA_133 },
119 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_P 119 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20277), PDC_UDMA_133 },
120 120
121 { } /* terminate list */ 121 { } /* terminate list */
122 }; 122 };
123 123
124 static struct pci_driver pdc2027x_pci_driver = 124 static struct pci_driver pdc2027x_pci_driver = {
125 .name = DRV_NAME, 125 .name = DRV_NAME,
126 .id_table = pdc2027x_pci 126 .id_table = pdc2027x_pci_tbl,
127 .probe = pdc2027x_ini 127 .probe = pdc2027x_init_one,
128 .remove = ata_pci_remo 128 .remove = ata_pci_remove_one,
129 }; 129 };
130 130
131 static struct scsi_host_template pdc2027x_sht 131 static struct scsi_host_template pdc2027x_sht = {
132 ATA_BMDMA_SHT(DRV_NAME), !! 132 .module = THIS_MODULE,
>> 133 .name = DRV_NAME,
>> 134 .ioctl = ata_scsi_ioctl,
>> 135 .queuecommand = ata_scsi_queuecmd,
>> 136 .can_queue = ATA_DEF_QUEUE,
>> 137 .this_id = ATA_SHT_THIS_ID,
>> 138 .sg_tablesize = LIBATA_MAX_PRD,
>> 139 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
>> 140 .emulated = ATA_SHT_EMULATED,
>> 141 .use_clustering = ATA_SHT_USE_CLUSTERING,
>> 142 .proc_name = DRV_NAME,
>> 143 .dma_boundary = ATA_DMA_BOUNDARY,
>> 144 .slave_configure = ata_scsi_slave_config,
>> 145 .slave_destroy = ata_scsi_slave_destroy,
>> 146 .bios_param = ata_std_bios_param,
133 }; 147 };
134 148
135 static struct ata_port_operations pdc2027x_pat 149 static struct ata_port_operations pdc2027x_pata100_ops = {
136 .inherits = &ata_bmdma_p !! 150 .mode_filter = ata_pci_default_filter,
>> 151
>> 152 .tf_load = ata_tf_load,
>> 153 .tf_read = ata_tf_read,
>> 154 .check_status = ata_check_status,
>> 155 .exec_command = ata_exec_command,
>> 156 .dev_select = ata_std_dev_select,
>> 157
137 .check_atapi_dma = pdc2027x_che 158 .check_atapi_dma = pdc2027x_check_atapi_dma,
>> 159 .bmdma_setup = ata_bmdma_setup,
>> 160 .bmdma_start = ata_bmdma_start,
>> 161 .bmdma_stop = ata_bmdma_stop,
>> 162 .bmdma_status = ata_bmdma_status,
>> 163 .qc_prep = ata_qc_prep,
>> 164 .qc_issue = ata_qc_issue_prot,
>> 165 .data_xfer = ata_data_xfer,
>> 166
>> 167 .freeze = ata_bmdma_freeze,
>> 168 .thaw = ata_bmdma_thaw,
>> 169 .error_handler = pdc2027x_error_handler,
>> 170 .post_internal_cmd = ata_bmdma_post_internal_cmd,
138 .cable_detect = pdc2027x_cab 171 .cable_detect = pdc2027x_cable_detect,
139 .prereset = pdc2027x_pre !! 172
>> 173 .irq_clear = ata_bmdma_irq_clear,
>> 174 .irq_on = ata_irq_on,
>> 175
>> 176 .port_start = ata_sff_port_start,
140 }; 177 };
141 178
142 static struct ata_port_operations pdc2027x_pat 179 static struct ata_port_operations pdc2027x_pata133_ops = {
143 .inherits = &pdc2027x_pa <<
144 .mode_filter = pdc2027x_mod <<
145 .set_piomode = pdc2027x_set 180 .set_piomode = pdc2027x_set_piomode,
146 .set_dmamode = pdc2027x_set 181 .set_dmamode = pdc2027x_set_dmamode,
147 .set_mode = pdc2027x_set 182 .set_mode = pdc2027x_set_mode,
>> 183 .mode_filter = pdc2027x_mode_filter,
>> 184
>> 185 .tf_load = ata_tf_load,
>> 186 .tf_read = ata_tf_read,
>> 187 .check_status = ata_check_status,
>> 188 .exec_command = ata_exec_command,
>> 189 .dev_select = ata_std_dev_select,
>> 190
>> 191 .check_atapi_dma = pdc2027x_check_atapi_dma,
>> 192 .bmdma_setup = ata_bmdma_setup,
>> 193 .bmdma_start = ata_bmdma_start,
>> 194 .bmdma_stop = ata_bmdma_stop,
>> 195 .bmdma_status = ata_bmdma_status,
>> 196 .qc_prep = ata_qc_prep,
>> 197 .qc_issue = ata_qc_issue_prot,
>> 198 .data_xfer = ata_data_xfer,
>> 199
>> 200 .freeze = ata_bmdma_freeze,
>> 201 .thaw = ata_bmdma_thaw,
>> 202 .error_handler = pdc2027x_error_handler,
>> 203 .post_internal_cmd = ata_bmdma_post_internal_cmd,
>> 204 .cable_detect = pdc2027x_cable_detect,
>> 205
>> 206 .irq_clear = ata_bmdma_irq_clear,
>> 207 .irq_on = ata_irq_on,
>> 208
>> 209 .port_start = ata_sff_port_start,
148 }; 210 };
149 211
150 static struct ata_port_info pdc2027x_port_info 212 static struct ata_port_info pdc2027x_port_info[] = {
151 /* PDC_UDMA_100 */ 213 /* PDC_UDMA_100 */
152 { 214 {
153 .flags = ATA_FLAG_NO_ 215 .flags = ATA_FLAG_NO_LEGACY | ATA_FLAG_SLAVE_POSS |
154 ATA_FLAG_MMI 216 ATA_FLAG_MMIO,
155 .pio_mask = ATA_PIO4, !! 217 .pio_mask = 0x1f, /* pio0-4 */
156 .mwdma_mask = ATA_MWDMA2, !! 218 .mwdma_mask = 0x07, /* mwdma0-2 */
157 .udma_mask = ATA_UDMA5, !! 219 .udma_mask = ATA_UDMA5, /* udma0-5 */
158 .port_ops = &pdc2027x_pa 220 .port_ops = &pdc2027x_pata100_ops,
159 }, 221 },
160 /* PDC_UDMA_133 */ 222 /* PDC_UDMA_133 */
161 { 223 {
162 .flags = ATA_FLAG_NO_ 224 .flags = ATA_FLAG_NO_LEGACY | ATA_FLAG_SLAVE_POSS |
163 ATA_FLAG_MMI 225 ATA_FLAG_MMIO,
164 .pio_mask = ATA_PIO4, !! 226 .pio_mask = 0x1f, /* pio0-4 */
165 .mwdma_mask = ATA_MWDMA2, !! 227 .mwdma_mask = 0x07, /* mwdma0-2 */
166 .udma_mask = ATA_UDMA6, !! 228 .udma_mask = ATA_UDMA6, /* udma0-6 */
167 .port_ops = &pdc2027x_pa 229 .port_ops = &pdc2027x_pata133_ops,
168 }, 230 },
169 }; 231 };
170 232
171 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan, A 233 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan, Albert Lee");
172 MODULE_DESCRIPTION("libata driver module for P 234 MODULE_DESCRIPTION("libata driver module for Promise PDC20268 to PDC20277");
173 MODULE_LICENSE("GPL"); 235 MODULE_LICENSE("GPL");
174 MODULE_VERSION(DRV_VERSION); 236 MODULE_VERSION(DRV_VERSION);
175 MODULE_DEVICE_TABLE(pci, pdc2027x_pci_tbl); 237 MODULE_DEVICE_TABLE(pci, pdc2027x_pci_tbl);
176 238
177 /** 239 /**
178 * port_mmio - Get the MMIO address of PD 240 * port_mmio - Get the MMIO address of PDC2027x extended registers
179 * @ap: Port 241 * @ap: Port
180 * @offset: offset from mmio base 242 * @offset: offset from mmio base
181 */ 243 */
182 static inline void __iomem *port_mmio(struct a 244 static inline void __iomem *port_mmio(struct ata_port *ap, unsigned int offset)
183 { 245 {
184 return ap->host->iomap[PDC_MMIO_BAR] + 246 return ap->host->iomap[PDC_MMIO_BAR] + ap->port_no * 0x100 + offset;
185 } 247 }
186 248
187 /** 249 /**
188 * dev_mmio - Get the MMIO address of PDC 250 * dev_mmio - Get the MMIO address of PDC2027x extended registers
189 * @ap: Port 251 * @ap: Port
190 * @adev: device 252 * @adev: device
191 * @offset: offset from mmio base 253 * @offset: offset from mmio base
192 */ 254 */
193 static inline void __iomem *dev_mmio(struct at 255 static inline void __iomem *dev_mmio(struct ata_port *ap, struct ata_device *adev, unsigned int offset)
194 { 256 {
195 u8 adj = (adev->devno) ? 0x08 : 0x00; 257 u8 adj = (adev->devno) ? 0x08 : 0x00;
196 return port_mmio(ap, offset) + adj; 258 return port_mmio(ap, offset) + adj;
197 } 259 }
198 260
199 /** 261 /**
200 * pdc2027x_pata_cable_detect - Probe hos 262 * pdc2027x_pata_cable_detect - Probe host controller cable detect info
201 * @ap: Port for which cable detect info 263 * @ap: Port for which cable detect info is desired
202 * 264 *
203 * Read 80c cable indicator from Promise 265 * Read 80c cable indicator from Promise extended register.
204 * This register is latched when the syst 266 * This register is latched when the system is reset.
205 * 267 *
206 * LOCKING: 268 * LOCKING:
207 * None (inherited from caller). 269 * None (inherited from caller).
208 */ 270 */
209 static int pdc2027x_cable_detect(struct ata_po 271 static int pdc2027x_cable_detect(struct ata_port *ap)
210 { 272 {
211 u32 cgcr; 273 u32 cgcr;
212 274
213 /* check cable detect results */ 275 /* check cable detect results */
214 cgcr = ioread32(port_mmio(ap, PDC_GLOB 276 cgcr = ioread32(port_mmio(ap, PDC_GLOBAL_CTL));
215 if (cgcr & (1 << 26)) 277 if (cgcr & (1 << 26))
216 goto cbl40; 278 goto cbl40;
217 279
218 PDPRINTK("No cable or 80-conductor cab 280 PDPRINTK("No cable or 80-conductor cable on port %d\n", ap->port_no);
219 281
220 return ATA_CBL_PATA80; 282 return ATA_CBL_PATA80;
221 cbl40: 283 cbl40:
222 printk(KERN_INFO DRV_NAME ": 40-conduc 284 printk(KERN_INFO DRV_NAME ": 40-conductor cable detected on port %d\n", ap->port_no);
223 return ATA_CBL_PATA40; 285 return ATA_CBL_PATA40;
224 } 286 }
225 287
226 /** 288 /**
227 * pdc2027x_port_enabled - Check PDC ATA contr 289 * pdc2027x_port_enabled - Check PDC ATA control register to see whether the port is enabled.
228 * @ap: Port to check 290 * @ap: Port to check
229 */ 291 */
230 static inline int pdc2027x_port_enabled(struct 292 static inline int pdc2027x_port_enabled(struct ata_port *ap)
231 { 293 {
232 return ioread8(port_mmio(ap, PDC_ATA_C 294 return ioread8(port_mmio(ap, PDC_ATA_CTL)) & 0x02;
233 } 295 }
234 296
235 /** 297 /**
236 * pdc2027x_prereset - prereset for PATA 298 * pdc2027x_prereset - prereset for PATA host controller
237 * @link: Target link 299 * @link: Target link
238 * @deadline: deadline jiffies for the op 300 * @deadline: deadline jiffies for the operation
239 * 301 *
240 * Probeinit including cable detection. 302 * Probeinit including cable detection.
241 * 303 *
242 * LOCKING: 304 * LOCKING:
243 * None (inherited from caller). 305 * None (inherited from caller).
244 */ 306 */
245 307
246 static int pdc2027x_prereset(struct ata_link * 308 static int pdc2027x_prereset(struct ata_link *link, unsigned long deadline)
247 { 309 {
248 /* Check whether port enabled */ 310 /* Check whether port enabled */
249 if (!pdc2027x_port_enabled(link->ap)) 311 if (!pdc2027x_port_enabled(link->ap))
250 return -ENOENT; 312 return -ENOENT;
251 return ata_sff_prereset(link, deadline !! 313 return ata_std_prereset(link, deadline);
>> 314 }
>> 315
>> 316 /**
>> 317 * pdc2027x_error_handler - Perform reset on PATA port and classify
>> 318 * @ap: Port to reset
>> 319 *
>> 320 * Reset PATA phy and classify attached devices.
>> 321 *
>> 322 * LOCKING:
>> 323 * None (inherited from caller).
>> 324 */
>> 325
>> 326 static void pdc2027x_error_handler(struct ata_port *ap)
>> 327 {
>> 328 ata_bmdma_drive_eh(ap, pdc2027x_prereset, ata_std_softreset, NULL, ata_std_postreset);
252 } 329 }
253 330
254 /** 331 /**
255 * pdc2720x_mode_filter - mode s 332 * pdc2720x_mode_filter - mode selection filter
256 * @adev: ATA device 333 * @adev: ATA device
257 * @mask: list of modes proposed 334 * @mask: list of modes proposed
258 * 335 *
259 * Block UDMA on devices that cause troub 336 * Block UDMA on devices that cause trouble with this controller.
260 */ 337 */
261 338
262 static unsigned long pdc2027x_mode_filter(stru 339 static unsigned long pdc2027x_mode_filter(struct ata_device *adev, unsigned long mask)
263 { 340 {
264 unsigned char model_num[ATA_ID_PROD_LE 341 unsigned char model_num[ATA_ID_PROD_LEN + 1];
265 struct ata_device *pair = ata_dev_pair 342 struct ata_device *pair = ata_dev_pair(adev);
266 343
267 if (adev->class != ATA_DEV_ATA || adev 344 if (adev->class != ATA_DEV_ATA || adev->devno == 0 || pair == NULL)
268 return ata_bmdma_mode_filter(a !! 345 return ata_pci_default_filter(adev, mask);
269 346
270 /* Check for slave of a Maxtor at UDMA 347 /* Check for slave of a Maxtor at UDMA6 */
271 ata_id_c_string(pair->id, model_num, A 348 ata_id_c_string(pair->id, model_num, ATA_ID_PROD,
272 ATA_ID_PROD_LEN + 1) 349 ATA_ID_PROD_LEN + 1);
273 /* If the master is a maxtor in UDMA6 350 /* If the master is a maxtor in UDMA6 then the slave should not use UDMA 6 */
274 if (strstr(model_num, "Maxtor") == NUL 351 if (strstr(model_num, "Maxtor") == NULL && pair->dma_mode == XFER_UDMA_6)
275 mask &= ~ (1 << (6 + ATA_SHIFT 352 mask &= ~ (1 << (6 + ATA_SHIFT_UDMA));
276 353
277 return ata_bmdma_mode_filter(adev, mas !! 354 return ata_pci_default_filter(adev, mask);
278 } 355 }
279 356
280 /** 357 /**
281 * pdc2027x_set_piomode - Initialize host 358 * pdc2027x_set_piomode - Initialize host controller PATA PIO timings
282 * @ap: Port to configure 359 * @ap: Port to configure
283 * @adev: um 360 * @adev: um
>> 361 * @pio: PIO mode, 0 - 4
284 * 362 *
285 * Set PIO mode for device. 363 * Set PIO mode for device.
286 * 364 *
287 * LOCKING: 365 * LOCKING:
288 * None (inherited from caller). 366 * None (inherited from caller).
289 */ 367 */
290 368
291 static void pdc2027x_set_piomode(struct ata_po 369 static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev)
292 { 370 {
293 unsigned int pio = adev->pio_mode - XF 371 unsigned int pio = adev->pio_mode - XFER_PIO_0;
294 u32 ctcr0, ctcr1; 372 u32 ctcr0, ctcr1;
295 373
296 PDPRINTK("adev->pio_mode[%X]\n", adev- 374 PDPRINTK("adev->pio_mode[%X]\n", adev->pio_mode);
297 375
298 /* Sanity check */ 376 /* Sanity check */
299 if (pio > 4) { 377 if (pio > 4) {
300 printk(KERN_ERR DRV_NAME ": Un 378 printk(KERN_ERR DRV_NAME ": Unknown pio mode [%d] ignored\n", pio);
301 return; 379 return;
302 380
303 } 381 }
304 382
305 /* Set the PIO timing registers using 383 /* Set the PIO timing registers using value table for 133MHz */
306 PDPRINTK("Set pio regs... \n"); 384 PDPRINTK("Set pio regs... \n");
307 385
308 ctcr0 = ioread32(dev_mmio(ap, adev, PD 386 ctcr0 = ioread32(dev_mmio(ap, adev, PDC_CTCR0));
309 ctcr0 &= 0xffff0000; 387 ctcr0 &= 0xffff0000;
310 ctcr0 |= pdc2027x_pio_timing_tbl[pio]. 388 ctcr0 |= pdc2027x_pio_timing_tbl[pio].value0 |
311 (pdc2027x_pio_timing_tbl[pio]. 389 (pdc2027x_pio_timing_tbl[pio].value1 << 8);
312 iowrite32(ctcr0, dev_mmio(ap, adev, PD 390 iowrite32(ctcr0, dev_mmio(ap, adev, PDC_CTCR0));
313 391
314 ctcr1 = ioread32(dev_mmio(ap, adev, PD 392 ctcr1 = ioread32(dev_mmio(ap, adev, PDC_CTCR1));
315 ctcr1 &= 0x00ffffff; 393 ctcr1 &= 0x00ffffff;
316 ctcr1 |= (pdc2027x_pio_timing_tbl[pio] 394 ctcr1 |= (pdc2027x_pio_timing_tbl[pio].value2 << 24);
317 iowrite32(ctcr1, dev_mmio(ap, adev, PD 395 iowrite32(ctcr1, dev_mmio(ap, adev, PDC_CTCR1));
318 396
319 PDPRINTK("Set pio regs done\n"); 397 PDPRINTK("Set pio regs done\n");
320 398
321 PDPRINTK("Set to pio mode[%u] \n", pio 399 PDPRINTK("Set to pio mode[%u] \n", pio);
322 } 400 }
323 401
324 /** 402 /**
325 * pdc2027x_set_dmamode - Initialize host 403 * pdc2027x_set_dmamode - Initialize host controller PATA UDMA timings
326 * @ap: Port to configure 404 * @ap: Port to configure
327 * @adev: um 405 * @adev: um
>> 406 * @udma: udma mode, XFER_UDMA_0 to XFER_UDMA_6
328 * 407 *
329 * Set UDMA mode for device. 408 * Set UDMA mode for device.
330 * 409 *
331 * LOCKING: 410 * LOCKING:
332 * None (inherited from caller). 411 * None (inherited from caller).
333 */ 412 */
334 static void pdc2027x_set_dmamode(struct ata_po 413 static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev)
335 { 414 {
336 unsigned int dma_mode = adev->dma_mode 415 unsigned int dma_mode = adev->dma_mode;
337 u32 ctcr0, ctcr1; 416 u32 ctcr0, ctcr1;
338 417
339 if ((dma_mode >= XFER_UDMA_0) && 418 if ((dma_mode >= XFER_UDMA_0) &&
340 (dma_mode <= XFER_UDMA_6)) { 419 (dma_mode <= XFER_UDMA_6)) {
341 /* Set the UDMA timing registe 420 /* Set the UDMA timing registers with value table for 133MHz */
342 unsigned int udma_mode = dma_m 421 unsigned int udma_mode = dma_mode & 0x07;
343 422
344 if (dma_mode == XFER_UDMA_2) { 423 if (dma_mode == XFER_UDMA_2) {
345 /* 424 /*
346 * Turn off tHOLD. 425 * Turn off tHOLD.
347 * If tHOLD is '1', th 426 * If tHOLD is '1', the hardware will add half clock for data hold time.
348 * This code segment s 427 * This code segment seems to be no effect. tHOLD will be overwritten below.
349 */ 428 */
350 ctcr1 = ioread32(dev_m 429 ctcr1 = ioread32(dev_mmio(ap, adev, PDC_CTCR1));
351 iowrite32(ctcr1 & ~(1 430 iowrite32(ctcr1 & ~(1 << 7), dev_mmio(ap, adev, PDC_CTCR1));
352 } 431 }
353 432
354 PDPRINTK("Set udma regs... \n" 433 PDPRINTK("Set udma regs... \n");
355 434
356 ctcr1 = ioread32(dev_mmio(ap, 435 ctcr1 = ioread32(dev_mmio(ap, adev, PDC_CTCR1));
357 ctcr1 &= 0xff000000; 436 ctcr1 &= 0xff000000;
358 ctcr1 |= pdc2027x_udma_timing_ 437 ctcr1 |= pdc2027x_udma_timing_tbl[udma_mode].value0 |
359 (pdc2027x_udma_timing_ 438 (pdc2027x_udma_timing_tbl[udma_mode].value1 << 8) |
360 (pdc2027x_udma_timing_ 439 (pdc2027x_udma_timing_tbl[udma_mode].value2 << 16);
361 iowrite32(ctcr1, dev_mmio(ap, 440 iowrite32(ctcr1, dev_mmio(ap, adev, PDC_CTCR1));
362 441
363 PDPRINTK("Set udma regs done\n 442 PDPRINTK("Set udma regs done\n");
364 443
365 PDPRINTK("Set to udma mode[%u] 444 PDPRINTK("Set to udma mode[%u] \n", udma_mode);
366 445
367 } else if ((dma_mode >= XFER_MW_DMA_0 446 } else if ((dma_mode >= XFER_MW_DMA_0) &&
368 (dma_mode <= XFER_MW_DMA_2) 447 (dma_mode <= XFER_MW_DMA_2)) {
369 /* Set the MDMA timing registe 448 /* Set the MDMA timing registers with value table for 133MHz */
370 unsigned int mdma_mode = dma_m 449 unsigned int mdma_mode = dma_mode & 0x07;
371 450
372 PDPRINTK("Set mdma regs... \n" 451 PDPRINTK("Set mdma regs... \n");
373 ctcr0 = ioread32(dev_mmio(ap, 452 ctcr0 = ioread32(dev_mmio(ap, adev, PDC_CTCR0));
374 453
375 ctcr0 &= 0x0000ffff; 454 ctcr0 &= 0x0000ffff;
376 ctcr0 |= (pdc2027x_mdma_timing 455 ctcr0 |= (pdc2027x_mdma_timing_tbl[mdma_mode].value0 << 16) |
377 (pdc2027x_mdma_timing_ 456 (pdc2027x_mdma_timing_tbl[mdma_mode].value1 << 24);
378 457
379 iowrite32(ctcr0, dev_mmio(ap, 458 iowrite32(ctcr0, dev_mmio(ap, adev, PDC_CTCR0));
380 PDPRINTK("Set mdma regs done\n 459 PDPRINTK("Set mdma regs done\n");
381 460
382 PDPRINTK("Set to mdma mode[%u] 461 PDPRINTK("Set to mdma mode[%u] \n", mdma_mode);
383 } else { 462 } else {
384 printk(KERN_ERR DRV_NAME ": Un 463 printk(KERN_ERR DRV_NAME ": Unknown dma mode [%u] ignored\n", dma_mode);
385 } 464 }
386 } 465 }
387 466
388 /** 467 /**
389 * pdc2027x_set_mode - Set the timing reg 468 * pdc2027x_set_mode - Set the timing registers back to correct values.
390 * @link: link to configure 469 * @link: link to configure
391 * @r_failed: Returned device for failure 470 * @r_failed: Returned device for failure
392 * 471 *
393 * The pdc2027x hardware will look at "SE 472 * The pdc2027x hardware will look at "SET FEATURES" and change the timing registers
394 * automatically. The values set by the h 473 * automatically. The values set by the hardware might be incorrect, under 133Mhz PLL.
395 * This function overwrites the possibly 474 * This function overwrites the possibly incorrect values set by the hardware to be correct.
396 */ 475 */
397 static int pdc2027x_set_mode(struct ata_link * 476 static int pdc2027x_set_mode(struct ata_link *link, struct ata_device **r_failed)
398 { 477 {
399 struct ata_port *ap = link->ap; 478 struct ata_port *ap = link->ap;
400 struct ata_device *dev; 479 struct ata_device *dev;
401 int rc; 480 int rc;
402 481
403 rc = ata_do_set_mode(link, r_failed); 482 rc = ata_do_set_mode(link, r_failed);
404 if (rc < 0) 483 if (rc < 0)
405 return rc; 484 return rc;
406 485
407 ata_for_each_dev(dev, link, ENABLED) { !! 486 ata_link_for_each_dev(dev, link) {
408 pdc2027x_set_piomode(ap, dev); !! 487 if (ata_dev_enabled(dev)) {
409 488
410 /* !! 489 pdc2027x_set_piomode(ap, dev);
411 * Enable prefetch if the devi !! 490
412 */ !! 491 /*
413 if (dev->xfer_shift == ATA_SHI !! 492 * Enable prefetch if the device support PIO only.
414 u32 ctcr1 = ioread32(d !! 493 */
415 ctcr1 |= (1 << 25); !! 494 if (dev->xfer_shift == ATA_SHIFT_PIO) {
416 iowrite32(ctcr1, dev_m !! 495 u32 ctcr1 = ioread32(dev_mmio(ap, dev, PDC_CTCR1));
417 !! 496 ctcr1 |= (1 << 25);
418 PDPRINTK("Turn on pref !! 497 iowrite32(ctcr1, dev_mmio(ap, dev, PDC_CTCR1));
419 } else { !! 498
420 pdc2027x_set_dmamode(a !! 499 PDPRINTK("Turn on prefetch\n");
>> 500 } else {
>> 501 pdc2027x_set_dmamode(ap, dev);
>> 502 }
421 } 503 }
422 } 504 }
423 return 0; 505 return 0;
424 } 506 }
425 507
426 /** 508 /**
427 * pdc2027x_check_atapi_dma - Check wheth 509 * pdc2027x_check_atapi_dma - Check whether ATAPI DMA can be supported for this command
428 * @qc: Metadata associated with taskfile 510 * @qc: Metadata associated with taskfile to check
429 * 511 *
430 * LOCKING: 512 * LOCKING:
431 * None (inherited from caller). 513 * None (inherited from caller).
432 * 514 *
433 * RETURNS: 0 when ATAPI DMA can be used 515 * RETURNS: 0 when ATAPI DMA can be used
434 * 1 otherwise 516 * 1 otherwise
435 */ 517 */
436 static int pdc2027x_check_atapi_dma(struct ata 518 static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc)
437 { 519 {
438 struct scsi_cmnd *cmd = qc->scsicmd; 520 struct scsi_cmnd *cmd = qc->scsicmd;
439 u8 *scsicmd = cmd->cmnd; 521 u8 *scsicmd = cmd->cmnd;
440 int rc = 1; /* atapi dma off by defaul 522 int rc = 1; /* atapi dma off by default */
441 523
442 /* 524 /*
443 * This workaround is from Promise's G 525 * This workaround is from Promise's GPL driver.
444 * If ATAPI DMA is used for commands n 526 * If ATAPI DMA is used for commands not in the
445 * following white list, say MODE_SENS 527 * following white list, say MODE_SENSE and REQUEST_SENSE,
446 * pdc2027x might hit the irq lost pro 528 * pdc2027x might hit the irq lost problem.
447 */ 529 */
448 switch (scsicmd[0]) { 530 switch (scsicmd[0]) {
449 case READ_10: 531 case READ_10:
450 case WRITE_10: 532 case WRITE_10:
451 case READ_12: 533 case READ_12:
452 case WRITE_12: 534 case WRITE_12:
453 case READ_6: 535 case READ_6:
454 case WRITE_6: 536 case WRITE_6:
455 case 0xad: /* READ_DVD_STRUCTURE */ 537 case 0xad: /* READ_DVD_STRUCTURE */
456 case 0xbe: /* READ_CD */ 538 case 0xbe: /* READ_CD */
457 /* ATAPI DMA is ok */ 539 /* ATAPI DMA is ok */
458 rc = 0; 540 rc = 0;
459 break; 541 break;
460 default: 542 default:
461 ; 543 ;
462 } 544 }
463 545
464 return rc; 546 return rc;
465 } 547 }
466 548
467 /** 549 /**
468 * pdc_read_counter - Read the ctr counter 550 * pdc_read_counter - Read the ctr counter
469 * @host: target ATA host 551 * @host: target ATA host
470 */ 552 */
471 553
472 static long pdc_read_counter(struct ata_host * 554 static long pdc_read_counter(struct ata_host *host)
473 { 555 {
474 void __iomem *mmio_base = host->iomap[ 556 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR];
475 long counter; 557 long counter;
476 int retry = 1; 558 int retry = 1;
477 u32 bccrl, bccrh, bccrlv, bccrhv; 559 u32 bccrl, bccrh, bccrlv, bccrhv;
478 560
479 retry: 561 retry:
480 bccrl = ioread32(mmio_base + PDC_BYTE_ 562 bccrl = ioread32(mmio_base + PDC_BYTE_COUNT) & 0x7fff;
481 bccrh = ioread32(mmio_base + PDC_BYTE_ 563 bccrh = ioread32(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff;
482 564
483 /* Read the counter values again for v 565 /* Read the counter values again for verification */
484 bccrlv = ioread32(mmio_base + PDC_BYTE 566 bccrlv = ioread32(mmio_base + PDC_BYTE_COUNT) & 0x7fff;
485 bccrhv = ioread32(mmio_base + PDC_BYTE 567 bccrhv = ioread32(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff;
486 568
487 counter = (bccrh << 15) | bccrl; 569 counter = (bccrh << 15) | bccrl;
488 570
489 PDPRINTK("bccrh [%X] bccrl [%X]\n", bc 571 PDPRINTK("bccrh [%X] bccrl [%X]\n", bccrh, bccrl);
490 PDPRINTK("bccrhv[%X] bccrlv[%X]\n", bc 572 PDPRINTK("bccrhv[%X] bccrlv[%X]\n", bccrhv, bccrlv);
491 573
492 /* 574 /*
493 * The 30-bit decreasing counter are r 575 * The 30-bit decreasing counter are read by 2 pieces.
494 * Incorrect value may be read when bo 576 * Incorrect value may be read when both bccrh and bccrl are changing.
495 * Ex. When 7900 decrease to 78FF, wro 577 * Ex. When 7900 decrease to 78FF, wrong value 7800 might be read.
496 */ 578 */
497 if (retry && !(bccrh == bccrhv && bccr 579 if (retry && !(bccrh == bccrhv && bccrl >= bccrlv)) {
498 retry--; 580 retry--;
499 PDPRINTK("rereading counter\n" 581 PDPRINTK("rereading counter\n");
500 goto retry; 582 goto retry;
501 } 583 }
502 584
503 return counter; 585 return counter;
504 } 586 }
505 587
506 /** 588 /**
507 * adjust_pll - Adjust the PLL input clock in 589 * adjust_pll - Adjust the PLL input clock in Hz.
508 * 590 *
509 * @pdc_controller: controller specific inform 591 * @pdc_controller: controller specific information
510 * @host: target ATA host 592 * @host: target ATA host
511 * @pll_clock: The input of PLL in HZ 593 * @pll_clock: The input of PLL in HZ
512 */ 594 */
513 static void pdc_adjust_pll(struct ata_host *ho 595 static void pdc_adjust_pll(struct ata_host *host, long pll_clock, unsigned int board_idx)
514 { 596 {
515 void __iomem *mmio_base = host->iomap[ 597 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR];
516 u16 pll_ctl; 598 u16 pll_ctl;
517 long pll_clock_khz = pll_clock / 1000; 599 long pll_clock_khz = pll_clock / 1000;
518 long pout_required = board_idx? PDC_13 600 long pout_required = board_idx? PDC_133_MHZ:PDC_100_MHZ;
519 long ratio = pout_required / pll_clock 601 long ratio = pout_required / pll_clock_khz;
520 int F, R; 602 int F, R;
521 603
522 /* Sanity check */ 604 /* Sanity check */
523 if (unlikely(pll_clock_khz < 5000L || 605 if (unlikely(pll_clock_khz < 5000L || pll_clock_khz > 70000L)) {
524 printk(KERN_ERR DRV_NAME ": In 606 printk(KERN_ERR DRV_NAME ": Invalid PLL input clock %ldkHz, give up!\n", pll_clock_khz);
525 return; 607 return;
526 } 608 }
527 609
528 #ifdef PDC_DEBUG 610 #ifdef PDC_DEBUG
529 PDPRINTK("pout_required is %ld\n", pou 611 PDPRINTK("pout_required is %ld\n", pout_required);
530 612
531 /* Show the current clock value of PLL 613 /* Show the current clock value of PLL control register
532 * (maybe already configured by the fi 614 * (maybe already configured by the firmware)
533 */ 615 */
534 pll_ctl = ioread16(mmio_base + PDC_PLL 616 pll_ctl = ioread16(mmio_base + PDC_PLL_CTL);
535 617
536 PDPRINTK("pll_ctl[%X]\n", pll_ctl); 618 PDPRINTK("pll_ctl[%X]\n", pll_ctl);
537 #endif 619 #endif
538 620
539 /* 621 /*
540 * Calculate the ratio of F, R and OD 622 * Calculate the ratio of F, R and OD
541 * POUT = (F + 2) / (( R + 2) * NO) 623 * POUT = (F + 2) / (( R + 2) * NO)
542 */ 624 */
543 if (ratio < 8600L) { /* 8.6x */ 625 if (ratio < 8600L) { /* 8.6x */
544 /* Using NO = 0x01, R = 0x0D * 626 /* Using NO = 0x01, R = 0x0D */
545 R = 0x0d; 627 R = 0x0d;
546 } else if (ratio < 12900L) { /* 12.9x 628 } else if (ratio < 12900L) { /* 12.9x */
547 /* Using NO = 0x01, R = 0x08 * 629 /* Using NO = 0x01, R = 0x08 */
548 R = 0x08; 630 R = 0x08;
549 } else if (ratio < 16100L) { /* 16.1x 631 } else if (ratio < 16100L) { /* 16.1x */
550 /* Using NO = 0x01, R = 0x06 * 632 /* Using NO = 0x01, R = 0x06 */
551 R = 0x06; 633 R = 0x06;
552 } else if (ratio < 64000L) { /* 64x */ 634 } else if (ratio < 64000L) { /* 64x */
553 R = 0x00; 635 R = 0x00;
554 } else { 636 } else {
555 /* Invalid ratio */ 637 /* Invalid ratio */
556 printk(KERN_ERR DRV_NAME ": In 638 printk(KERN_ERR DRV_NAME ": Invalid ratio %ld, give up!\n", ratio);
557 return; 639 return;
558 } 640 }
559 641
560 F = (ratio * (R+2)) / 1000 - 2; 642 F = (ratio * (R+2)) / 1000 - 2;
561 643
562 if (unlikely(F < 0 || F > 127)) { 644 if (unlikely(F < 0 || F > 127)) {
563 /* Invalid F */ 645 /* Invalid F */
564 printk(KERN_ERR DRV_NAME ": F[ 646 printk(KERN_ERR DRV_NAME ": F[%d] invalid!\n", F);
565 return; 647 return;
566 } 648 }
567 649
568 PDPRINTK("F[%d] R[%d] ratio*1000[%ld]\ 650 PDPRINTK("F[%d] R[%d] ratio*1000[%ld]\n", F, R, ratio);
569 651
570 pll_ctl = (R << 8) | F; 652 pll_ctl = (R << 8) | F;
571 653
572 PDPRINTK("Writing pll_ctl[%X]\n", pll_ 654 PDPRINTK("Writing pll_ctl[%X]\n", pll_ctl);
573 655
574 iowrite16(pll_ctl, mmio_base + PDC_PLL 656 iowrite16(pll_ctl, mmio_base + PDC_PLL_CTL);
575 ioread16(mmio_base + PDC_PLL_CTL); /* 657 ioread16(mmio_base + PDC_PLL_CTL); /* flush */
576 658
577 /* Wait the PLL circuit to be stable * 659 /* Wait the PLL circuit to be stable */
578 mdelay(30); 660 mdelay(30);
579 661
580 #ifdef PDC_DEBUG 662 #ifdef PDC_DEBUG
581 /* 663 /*
582 * Show the current clock value of PL 664 * Show the current clock value of PLL control register
583 * (maybe configured by the firmware) 665 * (maybe configured by the firmware)
584 */ 666 */
585 pll_ctl = ioread16(mmio_base + PDC_PLL 667 pll_ctl = ioread16(mmio_base + PDC_PLL_CTL);
586 668
587 PDPRINTK("pll_ctl[%X]\n", pll_ctl); 669 PDPRINTK("pll_ctl[%X]\n", pll_ctl);
588 #endif 670 #endif
589 671
590 return; 672 return;
591 } 673 }
592 674
593 /** 675 /**
594 * detect_pll_input_clock - Detect the PLL inp 676 * detect_pll_input_clock - Detect the PLL input clock in Hz.
595 * @host: target ATA host 677 * @host: target ATA host
596 * Ex. 16949000 on 33MHz PCI bus for pdc20275. 678 * Ex. 16949000 on 33MHz PCI bus for pdc20275.
597 * Half of the PCI clock. 679 * Half of the PCI clock.
598 */ 680 */
599 static long pdc_detect_pll_input_clock(struct 681 static long pdc_detect_pll_input_clock(struct ata_host *host)
600 { 682 {
601 void __iomem *mmio_base = host->iomap[ 683 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR];
602 u32 scr; 684 u32 scr;
603 long start_count, end_count; 685 long start_count, end_count;
604 struct timeval start_time, end_time; 686 struct timeval start_time, end_time;
605 long pll_clock, usec_elapsed; 687 long pll_clock, usec_elapsed;
606 688
607 /* Start the test mode */ 689 /* Start the test mode */
608 scr = ioread32(mmio_base + PDC_SYS_CTL 690 scr = ioread32(mmio_base + PDC_SYS_CTL);
609 PDPRINTK("scr[%X]\n", scr); 691 PDPRINTK("scr[%X]\n", scr);
610 iowrite32(scr | (0x01 << 14), mmio_bas 692 iowrite32(scr | (0x01 << 14), mmio_base + PDC_SYS_CTL);
611 ioread32(mmio_base + PDC_SYS_CTL); /* 693 ioread32(mmio_base + PDC_SYS_CTL); /* flush */
612 694
613 /* Read current counter value */ 695 /* Read current counter value */
614 start_count = pdc_read_counter(host); 696 start_count = pdc_read_counter(host);
615 do_gettimeofday(&start_time); 697 do_gettimeofday(&start_time);
616 698
617 /* Let the counter run for 100 ms. */ 699 /* Let the counter run for 100 ms. */
618 mdelay(100); 700 mdelay(100);
619 701
620 /* Read the counter values again */ 702 /* Read the counter values again */
621 end_count = pdc_read_counter(host); 703 end_count = pdc_read_counter(host);
622 do_gettimeofday(&end_time); 704 do_gettimeofday(&end_time);
623 705
624 /* Stop the test mode */ 706 /* Stop the test mode */
625 scr = ioread32(mmio_base + PDC_SYS_CTL 707 scr = ioread32(mmio_base + PDC_SYS_CTL);
626 PDPRINTK("scr[%X]\n", scr); 708 PDPRINTK("scr[%X]\n", scr);
627 iowrite32(scr & ~(0x01 << 14), mmio_ba 709 iowrite32(scr & ~(0x01 << 14), mmio_base + PDC_SYS_CTL);
628 ioread32(mmio_base + PDC_SYS_CTL); /* 710 ioread32(mmio_base + PDC_SYS_CTL); /* flush */
629 711
630 /* calculate the input clock in Hz */ 712 /* calculate the input clock in Hz */
631 usec_elapsed = (end_time.tv_sec - star 713 usec_elapsed = (end_time.tv_sec - start_time.tv_sec) * 1000000 +
632 (end_time.tv_usec - start_time 714 (end_time.tv_usec - start_time.tv_usec);
633 715
634 pll_clock = ((start_count - end_count) 716 pll_clock = ((start_count - end_count) & 0x3fffffff) / 100 *
635 (100000000 / usec_elapsed); 717 (100000000 / usec_elapsed);
636 718
637 PDPRINTK("start[%ld] end[%ld] \n", sta 719 PDPRINTK("start[%ld] end[%ld] \n", start_count, end_count);
638 PDPRINTK("PLL input clock[%ld]Hz\n", p 720 PDPRINTK("PLL input clock[%ld]Hz\n", pll_clock);
639 721
640 return pll_clock; 722 return pll_clock;
641 } 723 }
642 724
643 /** 725 /**
644 * pdc_hardware_init - Initialize the hardware 726 * pdc_hardware_init - Initialize the hardware.
645 * @host: target ATA host 727 * @host: target ATA host
646 * @board_idx: board identifier 728 * @board_idx: board identifier
647 */ 729 */
648 static int pdc_hardware_init(struct ata_host * 730 static int pdc_hardware_init(struct ata_host *host, unsigned int board_idx)
649 { 731 {
650 long pll_clock; 732 long pll_clock;
651 733
652 /* 734 /*
653 * Detect PLL input clock rate. 735 * Detect PLL input clock rate.
654 * On some system, where PCI bus is ru 736 * On some system, where PCI bus is running at non-standard clock rate.
655 * Ex. 25MHz or 40MHz, we have to adju 737 * Ex. 25MHz or 40MHz, we have to adjust the cycle_time.
656 * The pdc20275 controller employs PLL 738 * The pdc20275 controller employs PLL circuit to help correct timing registers setting.
657 */ 739 */
658 pll_clock = pdc_detect_pll_input_clock 740 pll_clock = pdc_detect_pll_input_clock(host);
659 741
660 dev_printk(KERN_INFO, host->dev, "PLL 742 dev_printk(KERN_INFO, host->dev, "PLL input clock %ld kHz\n", pll_clock/1000);
661 743
662 /* Adjust PLL control register */ 744 /* Adjust PLL control register */
663 pdc_adjust_pll(host, pll_clock, board_ 745 pdc_adjust_pll(host, pll_clock, board_idx);
664 746
665 return 0; 747 return 0;
666 } 748 }
667 749
668 /** 750 /**
669 * pdc_ata_setup_port - setup the mmio address 751 * pdc_ata_setup_port - setup the mmio address
670 * @port: ata ioports to setup 752 * @port: ata ioports to setup
671 * @base: base address 753 * @base: base address
672 */ 754 */
673 static void pdc_ata_setup_port(struct ata_iopo 755 static void pdc_ata_setup_port(struct ata_ioports *port, void __iomem *base)
674 { 756 {
675 port->cmd_addr = 757 port->cmd_addr =
676 port->data_addr = base; 758 port->data_addr = base;
677 port->feature_addr = 759 port->feature_addr =
678 port->error_addr = base + 0x05; 760 port->error_addr = base + 0x05;
679 port->nsect_addr = base + 0x0a; 761 port->nsect_addr = base + 0x0a;
680 port->lbal_addr = base + 0x0f; 762 port->lbal_addr = base + 0x0f;
681 port->lbam_addr = base + 0x10; 763 port->lbam_addr = base + 0x10;
682 port->lbah_addr = base + 0x15; 764 port->lbah_addr = base + 0x15;
683 port->device_addr = base + 0x1a; 765 port->device_addr = base + 0x1a;
684 port->command_addr = 766 port->command_addr =
685 port->status_addr = base + 0x1f; 767 port->status_addr = base + 0x1f;
686 port->altstatus_addr = 768 port->altstatus_addr =
687 port->ctl_addr = base + 0x81a 769 port->ctl_addr = base + 0x81a;
688 } 770 }
689 771
690 /** 772 /**
691 * pdc2027x_init_one - PCI probe function 773 * pdc2027x_init_one - PCI probe function
692 * Called when an instance of PCI adapter is i 774 * Called when an instance of PCI adapter is inserted.
693 * This function checks whether the hardware i 775 * This function checks whether the hardware is supported,
694 * initialize hardware and register an instanc 776 * initialize hardware and register an instance of ata_host to
695 * libata. (implements struct pci_driver.prob 777 * libata. (implements struct pci_driver.probe() )
696 * 778 *
697 * @pdev: instance of pci_dev found 779 * @pdev: instance of pci_dev found
698 * @ent: matching entry in the id_tbl[] 780 * @ent: matching entry in the id_tbl[]
699 */ 781 */
700 static int __devinit pdc2027x_init_one(struct 782 static int __devinit pdc2027x_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
701 { 783 {
702 static int printed_version; 784 static int printed_version;
703 static const unsigned long cmd_offset[ 785 static const unsigned long cmd_offset[] = { 0x17c0, 0x15c0 };
704 static const unsigned long bmdma_offse 786 static const unsigned long bmdma_offset[] = { 0x1000, 0x1008 };
705 unsigned int board_idx = (unsigned int 787 unsigned int board_idx = (unsigned int) ent->driver_data;
706 const struct ata_port_info *ppi[] = 788 const struct ata_port_info *ppi[] =
707 { &pdc2027x_port_info[board_id 789 { &pdc2027x_port_info[board_idx], NULL };
708 struct ata_host *host; 790 struct ata_host *host;
709 void __iomem *mmio_base; 791 void __iomem *mmio_base;
710 int i, rc; 792 int i, rc;
711 793
712 if (!printed_version++) 794 if (!printed_version++)
713 dev_printk(KERN_DEBUG, &pdev-> 795 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
714 796
715 /* alloc host */ 797 /* alloc host */
716 host = ata_host_alloc_pinfo(&pdev->dev 798 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
717 if (!host) 799 if (!host)
718 return -ENOMEM; 800 return -ENOMEM;
719 801
720 /* acquire resources and fill host */ 802 /* acquire resources and fill host */
721 rc = pcim_enable_device(pdev); 803 rc = pcim_enable_device(pdev);
722 if (rc) 804 if (rc)
723 return rc; 805 return rc;
724 806
725 rc = pcim_iomap_regions(pdev, 1 << PDC 807 rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME);
726 if (rc) 808 if (rc)
727 return rc; 809 return rc;
728 host->iomap = pcim_iomap_table(pdev); 810 host->iomap = pcim_iomap_table(pdev);
729 811
730 rc = pci_set_dma_mask(pdev, ATA_DMA_MA 812 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
731 if (rc) 813 if (rc)
732 return rc; 814 return rc;
733 815
734 rc = pci_set_consistent_dma_mask(pdev, 816 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
735 if (rc) 817 if (rc)
736 return rc; 818 return rc;
737 819
738 mmio_base = host->iomap[PDC_MMIO_BAR]; 820 mmio_base = host->iomap[PDC_MMIO_BAR];
739 821
740 for (i = 0; i < 2; i++) { 822 for (i = 0; i < 2; i++) {
741 struct ata_port *ap = host->po 823 struct ata_port *ap = host->ports[i];
742 824
743 pdc_ata_setup_port(&ap->ioaddr 825 pdc_ata_setup_port(&ap->ioaddr, mmio_base + cmd_offset[i]);
744 ap->ioaddr.bmdma_addr = mmio_b 826 ap->ioaddr.bmdma_addr = mmio_base + bmdma_offset[i];
745 827
746 ata_port_pbar_desc(ap, PDC_MMI 828 ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio");
747 ata_port_pbar_desc(ap, PDC_MMI 829 ata_port_pbar_desc(ap, PDC_MMIO_BAR, cmd_offset[i], "cmd");
748 } 830 }
749 831
750 //pci_enable_intx(pdev); 832 //pci_enable_intx(pdev);
751 833
752 /* initialize adapter */ 834 /* initialize adapter */
753 if (pdc_hardware_init(host, board_idx) 835 if (pdc_hardware_init(host, board_idx) != 0)
754 return -EIO; 836 return -EIO;
755 837
756 pci_set_master(pdev); 838 pci_set_master(pdev);
757 return ata_host_activate(host, pdev->i !! 839 return ata_host_activate(host, pdev->irq, ata_interrupt, IRQF_SHARED,
758 IRQF_SHARED, !! 840 &pdc2027x_sht);
759 } 841 }
760 842
761 /** 843 /**
762 * pdc2027x_init - Called after this module is 844 * pdc2027x_init - Called after this module is loaded into the kernel.
763 */ 845 */
764 static int __init pdc2027x_init(void) 846 static int __init pdc2027x_init(void)
765 { 847 {
766 return pci_register_driver(&pdc2027x_p 848 return pci_register_driver(&pdc2027x_pci_driver);
767 } 849 }
768 850
769 /** 851 /**
770 * pdc2027x_exit - Called before this module u 852 * pdc2027x_exit - Called before this module unloaded from the kernel
771 */ 853 */
772 static void __exit pdc2027x_exit(void) 854 static void __exit pdc2027x_exit(void)
773 { 855 {
774 pci_unregister_driver(&pdc2027x_pci_dr 856 pci_unregister_driver(&pdc2027x_pci_driver);
775 } 857 }
776 858
777 module_init(pdc2027x_init); 859 module_init(pdc2027x_init);
778 module_exit(pdc2027x_exit); 860 module_exit(pdc2027x_exit);
779 861
|
This page was automatically generated by the
LXR engine.
|