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1 /* 1
2 * Promise PATA TX2/TX4/TX2000/133 IDE driver
3 *
4 * This program is free software; you can red
5 * modify it under the terms of the GNU Gener
6 * as published by the Free Software Foundati
7 * 2 of the License, or (at your option) any
8 *
9 * Ported to libata by:
10 * Albert Lee <albertcc@tw.ibm.com> IBM Corpo
11 *
12 * Copyright (C) 1998-2002 Andre
13 * Portions Copyright (C) 1999 Promise Techno
14 *
15 * Author: Frank Tiernan (frankt@promise.com)
16 * Released under terms of General Public Lic
17 *
18 *
19 * libata documentation is available via 'mak
20 * as Documentation/DocBook/libata.*
21 *
22 * Hardware information only available under
23 *
24 */
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28 #include <linux/init.h>
29 #include <linux/blkdev.h>
30 #include <linux/delay.h>
31 #include <linux/device.h>
32 #include <scsi/scsi.h>
33 #include <scsi/scsi_host.h>
34 #include <scsi/scsi_cmnd.h>
35 #include <linux/libata.h>
36
37 #define DRV_NAME "pata_pdc2027x"
38 #define DRV_VERSION "1.0"
39 #undef PDC_DEBUG
40
41 #ifdef PDC_DEBUG
42 #define PDPRINTK(fmt, args...) printk(KERN_ERR
43 #else
44 #define PDPRINTK(fmt, args...)
45 #endif
46
47 enum {
48 PDC_MMIO_BAR = 5,
49
50 PDC_UDMA_100 = 0,
51 PDC_UDMA_133 = 1,
52
53 PDC_100_MHZ = 100000000,
54 PDC_133_MHZ = 133333333,
55
56 PDC_SYS_CTL = 0x1100,
57 PDC_ATA_CTL = 0x1104,
58 PDC_GLOBAL_CTL = 0x1108,
59 PDC_CTCR0 = 0x110C,
60 PDC_CTCR1 = 0x1110,
61 PDC_BYTE_COUNT = 0x1120,
62 PDC_PLL_CTL = 0x1202,
63 };
64
65 static int pdc2027x_init_one(struct pci_dev *p
66 static int pdc2027x_prereset(struct ata_link *
67 static void pdc2027x_set_piomode(struct ata_po
68 static void pdc2027x_set_dmamode(struct ata_po
69 static int pdc2027x_check_atapi_dma(struct ata
70 static unsigned long pdc2027x_mode_filter(stru
71 static int pdc2027x_cable_detect(struct ata_po
72 static int pdc2027x_set_mode(struct ata_link *
73
74 /*
75 * ATA Timing Tables based on 133MHz controlle
76 * These tables are only used when the control
77 * If the controller is in 100MHz clock, the A
78 * set the timing registers automatically when
79 * is issued to the device. However, if the co
80 * the following tables must be used.
81 */
82 static struct pdc2027x_pio_timing {
83 u8 value0, value1, value2;
84 } pdc2027x_pio_timing_tbl [] = {
85 { 0xfb, 0x2b, 0xac }, /* PIO mode 0 */
86 { 0x46, 0x29, 0xa4 }, /* PIO mode 1 */
87 { 0x23, 0x26, 0x64 }, /* PIO mode 2 */
88 { 0x27, 0x0d, 0x35 }, /* PIO mode 3, I
89 { 0x23, 0x09, 0x25 }, /* PIO mode 4, I
90 };
91
92 static struct pdc2027x_mdma_timing {
93 u8 value0, value1;
94 } pdc2027x_mdma_timing_tbl [] = {
95 { 0xdf, 0x5f }, /* MDMA mode 0 */
96 { 0x6b, 0x27 }, /* MDMA mode 1 */
97 { 0x69, 0x25 }, /* MDMA mode 2 */
98 };
99
100 static struct pdc2027x_udma_timing {
101 u8 value0, value1, value2;
102 } pdc2027x_udma_timing_tbl [] = {
103 { 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 *
104 { 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 *
105 { 0x2a, 0x07, 0xcd }, /* UDMA mode 2 *
106 { 0x1a, 0x05, 0xcd }, /* UDMA mode 3 *
107 { 0x1a, 0x03, 0xcd }, /* UDMA mode 4 *
108 { 0x1a, 0x02, 0xcb }, /* UDMA mode 5 *
109 { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 *
110 };
111
112 static const struct pci_device_id pdc2027x_pci
113 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_P
114 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_P
115 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_P
116 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_P
117 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_P
118 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_P
119 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_P
120
121 { } /* terminate list */
122 };
123
124 static struct pci_driver pdc2027x_pci_driver =
125 .name = DRV_NAME,
126 .id_table = pdc2027x_pci
127 .probe = pdc2027x_ini
128 .remove = ata_pci_remo
129 };
130
131 static struct scsi_host_template pdc2027x_sht
132 ATA_BMDMA_SHT(DRV_NAME),
133 };
134
135 static struct ata_port_operations pdc2027x_pat
136 .inherits = &ata_bmdma_p
137 .check_atapi_dma = pdc2027x_che
138 .cable_detect = pdc2027x_cab
139 .prereset = pdc2027x_pre
140 };
141
142 static struct ata_port_operations pdc2027x_pat
143 .inherits = &pdc2027x_pa
144 .mode_filter = pdc2027x_mod
145 .set_piomode = pdc2027x_set
146 .set_dmamode = pdc2027x_set
147 .set_mode = pdc2027x_set
148 };
149
150 static struct ata_port_info pdc2027x_port_info
151 /* PDC_UDMA_100 */
152 {
153 .flags = ATA_FLAG_NO_
154 ATA_FLAG_MMI
155 .pio_mask = ATA_PIO4,
156 .mwdma_mask = ATA_MWDMA2,
157 .udma_mask = ATA_UDMA5,
158 .port_ops = &pdc2027x_pa
159 },
160 /* PDC_UDMA_133 */
161 {
162 .flags = ATA_FLAG_NO_
163 ATA_FLAG_MMI
164 .pio_mask = ATA_PIO4,
165 .mwdma_mask = ATA_MWDMA2,
166 .udma_mask = ATA_UDMA6,
167 .port_ops = &pdc2027x_pa
168 },
169 };
170
171 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan, A
172 MODULE_DESCRIPTION("libata driver module for P
173 MODULE_LICENSE("GPL");
174 MODULE_VERSION(DRV_VERSION);
175 MODULE_DEVICE_TABLE(pci, pdc2027x_pci_tbl);
176
177 /**
178 * port_mmio - Get the MMIO address of PD
179 * @ap: Port
180 * @offset: offset from mmio base
181 */
182 static inline void __iomem *port_mmio(struct a
183 {
184 return ap->host->iomap[PDC_MMIO_BAR] +
185 }
186
187 /**
188 * dev_mmio - Get the MMIO address of PDC
189 * @ap: Port
190 * @adev: device
191 * @offset: offset from mmio base
192 */
193 static inline void __iomem *dev_mmio(struct at
194 {
195 u8 adj = (adev->devno) ? 0x08 : 0x00;
196 return port_mmio(ap, offset) + adj;
197 }
198
199 /**
200 * pdc2027x_pata_cable_detect - Probe hos
201 * @ap: Port for which cable detect info
202 *
203 * Read 80c cable indicator from Promise
204 * This register is latched when the syst
205 *
206 * LOCKING:
207 * None (inherited from caller).
208 */
209 static int pdc2027x_cable_detect(struct ata_po
210 {
211 u32 cgcr;
212
213 /* check cable detect results */
214 cgcr = ioread32(port_mmio(ap, PDC_GLOB
215 if (cgcr & (1 << 26))
216 goto cbl40;
217
218 PDPRINTK("No cable or 80-conductor cab
219
220 return ATA_CBL_PATA80;
221 cbl40:
222 printk(KERN_INFO DRV_NAME ": 40-conduc
223 return ATA_CBL_PATA40;
224 }
225
226 /**
227 * pdc2027x_port_enabled - Check PDC ATA contr
228 * @ap: Port to check
229 */
230 static inline int pdc2027x_port_enabled(struct
231 {
232 return ioread8(port_mmio(ap, PDC_ATA_C
233 }
234
235 /**
236 * pdc2027x_prereset - prereset for PATA
237 * @link: Target link
238 * @deadline: deadline jiffies for the op
239 *
240 * Probeinit including cable detection.
241 *
242 * LOCKING:
243 * None (inherited from caller).
244 */
245
246 static int pdc2027x_prereset(struct ata_link *
247 {
248 /* Check whether port enabled */
249 if (!pdc2027x_port_enabled(link->ap))
250 return -ENOENT;
251 return ata_sff_prereset(link, deadline
252 }
253
254 /**
255 * pdc2720x_mode_filter - mode s
256 * @adev: ATA device
257 * @mask: list of modes proposed
258 *
259 * Block UDMA on devices that cause troub
260 */
261
262 static unsigned long pdc2027x_mode_filter(stru
263 {
264 unsigned char model_num[ATA_ID_PROD_LE
265 struct ata_device *pair = ata_dev_pair
266
267 if (adev->class != ATA_DEV_ATA || adev
268 return ata_bmdma_mode_filter(a
269
270 /* Check for slave of a Maxtor at UDMA
271 ata_id_c_string(pair->id, model_num, A
272 ATA_ID_PROD_LEN + 1)
273 /* If the master is a maxtor in UDMA6
274 if (strstr(model_num, "Maxtor") == NUL
275 mask &= ~ (1 << (6 + ATA_SHIFT
276
277 return ata_bmdma_mode_filter(adev, mas
278 }
279
280 /**
281 * pdc2027x_set_piomode - Initialize host
282 * @ap: Port to configure
283 * @adev: um
284 *
285 * Set PIO mode for device.
286 *
287 * LOCKING:
288 * None (inherited from caller).
289 */
290
291 static void pdc2027x_set_piomode(struct ata_po
292 {
293 unsigned int pio = adev->pio_mode - XF
294 u32 ctcr0, ctcr1;
295
296 PDPRINTK("adev->pio_mode[%X]\n", adev-
297
298 /* Sanity check */
299 if (pio > 4) {
300 printk(KERN_ERR DRV_NAME ": Un
301 return;
302
303 }
304
305 /* Set the PIO timing registers using
306 PDPRINTK("Set pio regs... \n");
307
308 ctcr0 = ioread32(dev_mmio(ap, adev, PD
309 ctcr0 &= 0xffff0000;
310 ctcr0 |= pdc2027x_pio_timing_tbl[pio].
311 (pdc2027x_pio_timing_tbl[pio].
312 iowrite32(ctcr0, dev_mmio(ap, adev, PD
313
314 ctcr1 = ioread32(dev_mmio(ap, adev, PD
315 ctcr1 &= 0x00ffffff;
316 ctcr1 |= (pdc2027x_pio_timing_tbl[pio]
317 iowrite32(ctcr1, dev_mmio(ap, adev, PD
318
319 PDPRINTK("Set pio regs done\n");
320
321 PDPRINTK("Set to pio mode[%u] \n", pio
322 }
323
324 /**
325 * pdc2027x_set_dmamode - Initialize host
326 * @ap: Port to configure
327 * @adev: um
328 *
329 * Set UDMA mode for device.
330 *
331 * LOCKING:
332 * None (inherited from caller).
333 */
334 static void pdc2027x_set_dmamode(struct ata_po
335 {
336 unsigned int dma_mode = adev->dma_mode
337 u32 ctcr0, ctcr1;
338
339 if ((dma_mode >= XFER_UDMA_0) &&
340 (dma_mode <= XFER_UDMA_6)) {
341 /* Set the UDMA timing registe
342 unsigned int udma_mode = dma_m
343
344 if (dma_mode == XFER_UDMA_2) {
345 /*
346 * Turn off tHOLD.
347 * If tHOLD is '1', th
348 * This code segment s
349 */
350 ctcr1 = ioread32(dev_m
351 iowrite32(ctcr1 & ~(1
352 }
353
354 PDPRINTK("Set udma regs... \n"
355
356 ctcr1 = ioread32(dev_mmio(ap,
357 ctcr1 &= 0xff000000;
358 ctcr1 |= pdc2027x_udma_timing_
359 (pdc2027x_udma_timing_
360 (pdc2027x_udma_timing_
361 iowrite32(ctcr1, dev_mmio(ap,
362
363 PDPRINTK("Set udma regs done\n
364
365 PDPRINTK("Set to udma mode[%u]
366
367 } else if ((dma_mode >= XFER_MW_DMA_0
368 (dma_mode <= XFER_MW_DMA_2)
369 /* Set the MDMA timing registe
370 unsigned int mdma_mode = dma_m
371
372 PDPRINTK("Set mdma regs... \n"
373 ctcr0 = ioread32(dev_mmio(ap,
374
375 ctcr0 &= 0x0000ffff;
376 ctcr0 |= (pdc2027x_mdma_timing
377 (pdc2027x_mdma_timing_
378
379 iowrite32(ctcr0, dev_mmio(ap,
380 PDPRINTK("Set mdma regs done\n
381
382 PDPRINTK("Set to mdma mode[%u]
383 } else {
384 printk(KERN_ERR DRV_NAME ": Un
385 }
386 }
387
388 /**
389 * pdc2027x_set_mode - Set the timing reg
390 * @link: link to configure
391 * @r_failed: Returned device for failure
392 *
393 * The pdc2027x hardware will look at "SE
394 * automatically. The values set by the h
395 * This function overwrites the possibly
396 */
397 static int pdc2027x_set_mode(struct ata_link *
398 {
399 struct ata_port *ap = link->ap;
400 struct ata_device *dev;
401 int rc;
402
403 rc = ata_do_set_mode(link, r_failed);
404 if (rc < 0)
405 return rc;
406
407 ata_for_each_dev(dev, link, ENABLED) {
408 pdc2027x_set_piomode(ap, dev);
409
410 /*
411 * Enable prefetch if the devi
412 */
413 if (dev->xfer_shift == ATA_SHI
414 u32 ctcr1 = ioread32(d
415 ctcr1 |= (1 << 25);
416 iowrite32(ctcr1, dev_m
417
418 PDPRINTK("Turn on pref
419 } else {
420 pdc2027x_set_dmamode(a
421 }
422 }
423 return 0;
424 }
425
426 /**
427 * pdc2027x_check_atapi_dma - Check wheth
428 * @qc: Metadata associated with taskfile
429 *
430 * LOCKING:
431 * None (inherited from caller).
432 *
433 * RETURNS: 0 when ATAPI DMA can be used
434 * 1 otherwise
435 */
436 static int pdc2027x_check_atapi_dma(struct ata
437 {
438 struct scsi_cmnd *cmd = qc->scsicmd;
439 u8 *scsicmd = cmd->cmnd;
440 int rc = 1; /* atapi dma off by defaul
441
442 /*
443 * This workaround is from Promise's G
444 * If ATAPI DMA is used for commands n
445 * following white list, say MODE_SENS
446 * pdc2027x might hit the irq lost pro
447 */
448 switch (scsicmd[0]) {
449 case READ_10:
450 case WRITE_10:
451 case READ_12:
452 case WRITE_12:
453 case READ_6:
454 case WRITE_6:
455 case 0xad: /* READ_DVD_STRUCTURE */
456 case 0xbe: /* READ_CD */
457 /* ATAPI DMA is ok */
458 rc = 0;
459 break;
460 default:
461 ;
462 }
463
464 return rc;
465 }
466
467 /**
468 * pdc_read_counter - Read the ctr counter
469 * @host: target ATA host
470 */
471
472 static long pdc_read_counter(struct ata_host *
473 {
474 void __iomem *mmio_base = host->iomap[
475 long counter;
476 int retry = 1;
477 u32 bccrl, bccrh, bccrlv, bccrhv;
478
479 retry:
480 bccrl = ioread32(mmio_base + PDC_BYTE_
481 bccrh = ioread32(mmio_base + PDC_BYTE_
482
483 /* Read the counter values again for v
484 bccrlv = ioread32(mmio_base + PDC_BYTE
485 bccrhv = ioread32(mmio_base + PDC_BYTE
486
487 counter = (bccrh << 15) | bccrl;
488
489 PDPRINTK("bccrh [%X] bccrl [%X]\n", bc
490 PDPRINTK("bccrhv[%X] bccrlv[%X]\n", bc
491
492 /*
493 * The 30-bit decreasing counter are r
494 * Incorrect value may be read when bo
495 * Ex. When 7900 decrease to 78FF, wro
496 */
497 if (retry && !(bccrh == bccrhv && bccr
498 retry--;
499 PDPRINTK("rereading counter\n"
500 goto retry;
501 }
502
503 return counter;
504 }
505
506 /**
507 * adjust_pll - Adjust the PLL input clock in
508 *
509 * @pdc_controller: controller specific inform
510 * @host: target ATA host
511 * @pll_clock: The input of PLL in HZ
512 */
513 static void pdc_adjust_pll(struct ata_host *ho
514 {
515 void __iomem *mmio_base = host->iomap[
516 u16 pll_ctl;
517 long pll_clock_khz = pll_clock / 1000;
518 long pout_required = board_idx? PDC_13
519 long ratio = pout_required / pll_clock
520 int F, R;
521
522 /* Sanity check */
523 if (unlikely(pll_clock_khz < 5000L ||
524 printk(KERN_ERR DRV_NAME ": In
525 return;
526 }
527
528 #ifdef PDC_DEBUG
529 PDPRINTK("pout_required is %ld\n", pou
530
531 /* Show the current clock value of PLL
532 * (maybe already configured by the fi
533 */
534 pll_ctl = ioread16(mmio_base + PDC_PLL
535
536 PDPRINTK("pll_ctl[%X]\n", pll_ctl);
537 #endif
538
539 /*
540 * Calculate the ratio of F, R and OD
541 * POUT = (F + 2) / (( R + 2) * NO)
542 */
543 if (ratio < 8600L) { /* 8.6x */
544 /* Using NO = 0x01, R = 0x0D *
545 R = 0x0d;
546 } else if (ratio < 12900L) { /* 12.9x
547 /* Using NO = 0x01, R = 0x08 *
548 R = 0x08;
549 } else if (ratio < 16100L) { /* 16.1x
550 /* Using NO = 0x01, R = 0x06 *
551 R = 0x06;
552 } else if (ratio < 64000L) { /* 64x */
553 R = 0x00;
554 } else {
555 /* Invalid ratio */
556 printk(KERN_ERR DRV_NAME ": In
557 return;
558 }
559
560 F = (ratio * (R+2)) / 1000 - 2;
561
562 if (unlikely(F < 0 || F > 127)) {
563 /* Invalid F */
564 printk(KERN_ERR DRV_NAME ": F[
565 return;
566 }
567
568 PDPRINTK("F[%d] R[%d] ratio*1000[%ld]\
569
570 pll_ctl = (R << 8) | F;
571
572 PDPRINTK("Writing pll_ctl[%X]\n", pll_
573
574 iowrite16(pll_ctl, mmio_base + PDC_PLL
575 ioread16(mmio_base + PDC_PLL_CTL); /*
576
577 /* Wait the PLL circuit to be stable *
578 mdelay(30);
579
580 #ifdef PDC_DEBUG
581 /*
582 * Show the current clock value of PL
583 * (maybe configured by the firmware)
584 */
585 pll_ctl = ioread16(mmio_base + PDC_PLL
586
587 PDPRINTK("pll_ctl[%X]\n", pll_ctl);
588 #endif
589
590 return;
591 }
592
593 /**
594 * detect_pll_input_clock - Detect the PLL inp
595 * @host: target ATA host
596 * Ex. 16949000 on 33MHz PCI bus for pdc20275.
597 * Half of the PCI clock.
598 */
599 static long pdc_detect_pll_input_clock(struct
600 {
601 void __iomem *mmio_base = host->iomap[
602 u32 scr;
603 long start_count, end_count;
604 struct timeval start_time, end_time;
605 long pll_clock, usec_elapsed;
606
607 /* Start the test mode */
608 scr = ioread32(mmio_base + PDC_SYS_CTL
609 PDPRINTK("scr[%X]\n", scr);
610 iowrite32(scr | (0x01 << 14), mmio_bas
611 ioread32(mmio_base + PDC_SYS_CTL); /*
612
613 /* Read current counter value */
614 start_count = pdc_read_counter(host);
615 do_gettimeofday(&start_time);
616
617 /* Let the counter run for 100 ms. */
618 mdelay(100);
619
620 /* Read the counter values again */
621 end_count = pdc_read_counter(host);
622 do_gettimeofday(&end_time);
623
624 /* Stop the test mode */
625 scr = ioread32(mmio_base + PDC_SYS_CTL
626 PDPRINTK("scr[%X]\n", scr);
627 iowrite32(scr & ~(0x01 << 14), mmio_ba
628 ioread32(mmio_base + PDC_SYS_CTL); /*
629
630 /* calculate the input clock in Hz */
631 usec_elapsed = (end_time.tv_sec - star
632 (end_time.tv_usec - start_time
633
634 pll_clock = ((start_count - end_count)
635 (100000000 / usec_elapsed);
636
637 PDPRINTK("start[%ld] end[%ld] \n", sta
638 PDPRINTK("PLL input clock[%ld]Hz\n", p
639
640 return pll_clock;
641 }
642
643 /**
644 * pdc_hardware_init - Initialize the hardware
645 * @host: target ATA host
646 * @board_idx: board identifier
647 */
648 static int pdc_hardware_init(struct ata_host *
649 {
650 long pll_clock;
651
652 /*
653 * Detect PLL input clock rate.
654 * On some system, where PCI bus is ru
655 * Ex. 25MHz or 40MHz, we have to adju
656 * The pdc20275 controller employs PLL
657 */
658 pll_clock = pdc_detect_pll_input_clock
659
660 dev_printk(KERN_INFO, host->dev, "PLL
661
662 /* Adjust PLL control register */
663 pdc_adjust_pll(host, pll_clock, board_
664
665 return 0;
666 }
667
668 /**
669 * pdc_ata_setup_port - setup the mmio address
670 * @port: ata ioports to setup
671 * @base: base address
672 */
673 static void pdc_ata_setup_port(struct ata_iopo
674 {
675 port->cmd_addr =
676 port->data_addr = base;
677 port->feature_addr =
678 port->error_addr = base + 0x05;
679 port->nsect_addr = base + 0x0a;
680 port->lbal_addr = base + 0x0f;
681 port->lbam_addr = base + 0x10;
682 port->lbah_addr = base + 0x15;
683 port->device_addr = base + 0x1a;
684 port->command_addr =
685 port->status_addr = base + 0x1f;
686 port->altstatus_addr =
687 port->ctl_addr = base + 0x81a
688 }
689
690 /**
691 * pdc2027x_init_one - PCI probe function
692 * Called when an instance of PCI adapter is i
693 * This function checks whether the hardware i
694 * initialize hardware and register an instanc
695 * libata. (implements struct pci_driver.prob
696 *
697 * @pdev: instance of pci_dev found
698 * @ent: matching entry in the id_tbl[]
699 */
700 static int __devinit pdc2027x_init_one(struct
701 {
702 static int printed_version;
703 static const unsigned long cmd_offset[
704 static const unsigned long bmdma_offse
705 unsigned int board_idx = (unsigned int
706 const struct ata_port_info *ppi[] =
707 { &pdc2027x_port_info[board_id
708 struct ata_host *host;
709 void __iomem *mmio_base;
710 int i, rc;
711
712 if (!printed_version++)
713 dev_printk(KERN_DEBUG, &pdev->
714
715 /* alloc host */
716 host = ata_host_alloc_pinfo(&pdev->dev
717 if (!host)
718 return -ENOMEM;
719
720 /* acquire resources and fill host */
721 rc = pcim_enable_device(pdev);
722 if (rc)
723 return rc;
724
725 rc = pcim_iomap_regions(pdev, 1 << PDC
726 if (rc)
727 return rc;
728 host->iomap = pcim_iomap_table(pdev);
729
730 rc = pci_set_dma_mask(pdev, ATA_DMA_MA
731 if (rc)
732 return rc;
733
734 rc = pci_set_consistent_dma_mask(pdev,
735 if (rc)
736 return rc;
737
738 mmio_base = host->iomap[PDC_MMIO_BAR];
739
740 for (i = 0; i < 2; i++) {
741 struct ata_port *ap = host->po
742
743 pdc_ata_setup_port(&ap->ioaddr
744 ap->ioaddr.bmdma_addr = mmio_b
745
746 ata_port_pbar_desc(ap, PDC_MMI
747 ata_port_pbar_desc(ap, PDC_MMI
748 }
749
750 //pci_enable_intx(pdev);
751
752 /* initialize adapter */
753 if (pdc_hardware_init(host, board_idx)
754 return -EIO;
755
756 pci_set_master(pdev);
757 return ata_host_activate(host, pdev->i
758 IRQF_SHARED,
759 }
760
761 /**
762 * pdc2027x_init - Called after this module is
763 */
764 static int __init pdc2027x_init(void)
765 {
766 return pci_register_driver(&pdc2027x_p
767 }
768
769 /**
770 * pdc2027x_exit - Called before this module u
771 */
772 static void __exit pdc2027x_exit(void)
773 {
774 pci_unregister_driver(&pdc2027x_pci_dr
775 }
776
777 module_init(pdc2027x_init);
778 module_exit(pdc2027x_exit);
779
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