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1 /* 1
2 * (C) 2001-2004 Dave Jones. <davej@codemonk
3 * (C) 2002 Padraig Brady. <padraig@antefact
4 *
5 * Licensed under the terms of the GNU GPL Li
6 * Based upon datasheets & sample CPUs kindly
7 *
8 * VIA have currently 3 different versions of
9 * Version 1 (Longhaul) uses the BCR2 MSR at
10 * It is present only in Samuel 1 (C5A), Sam
11 * Version 2 of longhaul is backward compatib
12 * LONGHAUL MSR for purpose of both frequenc
13 * Present in Samuel 2 (steppings 1-7 only)
14 * Version 3 of longhaul got renamed to Power
15 * to use only the POWERSAVER MSR at 0x110a.
16 * It is present in Ezra-T (C5M), Nehemiah (
17 * It's pretty much the same feature wise to
18 * there is provision for scaling FSB too, b
19 * too well in practice so we don't even try
20 *
21 * BIG FAT DISCLAIMER: Work in progress code.
22 */
23
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/moduleparam.h>
27 #include <linux/init.h>
28 #include <linux/cpufreq.h>
29 #include <linux/pci.h>
30 #include <linux/slab.h>
31 #include <linux/string.h>
32 #include <linux/delay.h>
33
34 #include <asm/msr.h>
35 #include <asm/timex.h>
36 #include <asm/io.h>
37 #include <asm/acpi.h>
38 #include <linux/acpi.h>
39 #include <acpi/processor.h>
40
41 #include "longhaul.h"
42
43 #define PFX "longhaul: "
44
45 #define TYPE_LONGHAUL_V1 1
46 #define TYPE_LONGHAUL_V2 2
47 #define TYPE_POWERSAVER 3
48
49 #define CPU_SAMUEL 1
50 #define CPU_SAMUEL2 2
51 #define CPU_EZRA 3
52 #define CPU_EZRA_T 4
53 #define CPU_NEHEMIAH 5
54 #define CPU_NEHEMIAH_C 6
55
56 /* Flags */
57 #define USE_ACPI_C3 (1 << 1)
58 #define USE_NORTHBRIDGE (1 << 2)
59
60 static int cpu_model;
61 static unsigned int numscales=16;
62 static unsigned int fsb;
63
64 static const struct mV_pos *vrm_mV_table;
65 static const unsigned char *mV_vrm_table;
66
67 static unsigned int highest_speed, lowest_spee
68 static unsigned int minmult, maxmult;
69 static int can_scale_voltage;
70 static struct acpi_processor *pr = NULL;
71 static struct acpi_processor_cx *cx = NULL;
72 static u32 acpi_regs_addr;
73 static u8 longhaul_flags;
74 static unsigned int longhaul_index;
75
76 /* Module parameters */
77 static int scale_voltage;
78 static int disable_acpi_c3;
79 static int revid_errata;
80
81 #define dprintk(msg...) cpufreq_debug_printk(C
82
83
84 /* Clock ratios multiplied by 10 */
85 static int clock_ratio[32];
86 static int eblcr_table[32];
87 static int longhaul_version;
88 static struct cpufreq_frequency_table *longhau
89
90 #ifdef CONFIG_CPU_FREQ_DEBUG
91 static char speedbuffer[8];
92
93 static char *print_speed(int speed)
94 {
95 if (speed < 1000) {
96 snprintf(speedbuffer, sizeof(s
97 return speedbuffer;
98 }
99
100 if (speed%1000 == 0)
101 snprintf(speedbuffer, sizeof(s
102 "%dGHz", speed/1000);
103 else
104 snprintf(speedbuffer, sizeof(s
105 "%d.%dGHz", speed/1000
106
107 return speedbuffer;
108 }
109 #endif
110
111
112 static unsigned int calc_speed(int mult)
113 {
114 int khz;
115 khz = (mult/10)*fsb;
116 if (mult%10)
117 khz += fsb/2;
118 khz *= 1000;
119 return khz;
120 }
121
122
123 static int longhaul_get_cpu_mult(void)
124 {
125 unsigned long invalue=0,lo, hi;
126
127 rdmsr (MSR_IA32_EBL_CR_POWERON, lo, hi
128 invalue = (lo & (1<<22|1<<23|1<<24|1<<
129 if (longhaul_version==TYPE_LONGHAUL_V2
130 if (lo & (1<<27))
131 invalue+=16;
132 }
133 return eblcr_table[invalue];
134 }
135
136 /* For processor with BCR2 MSR */
137
138 static void do_longhaul1(unsigned int clock_ra
139 {
140 union msr_bcr2 bcr2;
141
142 rdmsrl(MSR_VIA_BCR2, bcr2.val);
143 /* Enable software clock multiplier */
144 bcr2.bits.ESOFTBF = 1;
145 bcr2.bits.CLOCKMUL = clock_ratio_index
146
147 /* Sync to timer tick */
148 safe_halt();
149 /* Change frequency on next halt or sl
150 wrmsrl(MSR_VIA_BCR2, bcr2.val);
151 /* Invoke transition */
152 ACPI_FLUSH_CPU_CACHE();
153 halt();
154
155 /* Disable software clock multiplier *
156 local_irq_disable();
157 rdmsrl(MSR_VIA_BCR2, bcr2.val);
158 bcr2.bits.ESOFTBF = 0;
159 wrmsrl(MSR_VIA_BCR2, bcr2.val);
160 }
161
162 /* For processor with Longhaul MSR */
163
164 static void do_powersaver(int cx_address, unsi
165 unsigned int dir)
166 {
167 union msr_longhaul longhaul;
168 u32 t;
169
170 rdmsrl(MSR_VIA_LONGHAUL, longhaul.val)
171 /* Setup new frequency */
172 if (!revid_errata)
173 longhaul.bits.RevisionKey = lo
174 else
175 longhaul.bits.RevisionKey = 0;
176 longhaul.bits.SoftBusRatio = clock_rat
177 longhaul.bits.SoftBusRatio4 = (clock_r
178 /* Setup new voltage */
179 if (can_scale_voltage)
180 longhaul.bits.SoftVID = (clock
181 /* Sync to timer tick */
182 safe_halt();
183 /* Raise voltage if necessary */
184 if (can_scale_voltage && dir) {
185 longhaul.bits.EnableSoftVID =
186 wrmsrl(MSR_VIA_LONGHAUL, longh
187 /* Change voltage */
188 if (!cx_address) {
189 ACPI_FLUSH_CPU_CACHE()
190 halt();
191 } else {
192 ACPI_FLUSH_CPU_CACHE()
193 /* Invoke C3 */
194 inb(cx_address);
195 /* Dummy op - must do
196 * read */
197 t = inl(acpi_gbl_FADT.
198 }
199 longhaul.bits.EnableSoftVID =
200 wrmsrl(MSR_VIA_LONGHAUL, longh
201 }
202
203 /* Change frequency on next halt or sl
204 longhaul.bits.EnableSoftBusRatio = 1;
205 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val)
206 if (!cx_address) {
207 ACPI_FLUSH_CPU_CACHE();
208 halt();
209 } else {
210 ACPI_FLUSH_CPU_CACHE();
211 /* Invoke C3 */
212 inb(cx_address);
213 /* Dummy op - must do somethin
214 t = inl(acpi_gbl_FADT.xpm_time
215 }
216 /* Disable bus ratio bit */
217 longhaul.bits.EnableSoftBusRatio = 0;
218 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val)
219
220 /* Reduce voltage if necessary */
221 if (can_scale_voltage && !dir) {
222 longhaul.bits.EnableSoftVID =
223 wrmsrl(MSR_VIA_LONGHAUL, longh
224 /* Change voltage */
225 if (!cx_address) {
226 ACPI_FLUSH_CPU_CACHE()
227 halt();
228 } else {
229 ACPI_FLUSH_CPU_CACHE()
230 /* Invoke C3 */
231 inb(cx_address);
232 /* Dummy op - must do
233 * read */
234 t = inl(acpi_gbl_FADT.
235 }
236 longhaul.bits.EnableSoftVID =
237 wrmsrl(MSR_VIA_LONGHAUL, longh
238 }
239 }
240
241 /**
242 * longhaul_set_cpu_frequency()
243 * @clock_ratio_index : bitpattern of the new
244 *
245 * Sets a new clock ratio.
246 */
247
248 static void longhaul_setstate(unsigned int tab
249 {
250 unsigned int clock_ratio_index;
251 int speed, mult;
252 struct cpufreq_freqs freqs;
253 unsigned long flags;
254 unsigned int pic1_mask, pic2_mask;
255 u16 bm_status = 0;
256 u32 bm_timeout = 1000;
257 unsigned int dir = 0;
258
259 clock_ratio_index = longhaul_table[tab
260 /* Safety precautions */
261 mult = clock_ratio[clock_ratio_index &
262 if (mult == -1)
263 return;
264 speed = calc_speed(mult);
265 if ((speed > highest_speed) || (speed
266 return;
267 /* Voltage transition before frequency
268 if (can_scale_voltage && longhaul_inde
269 dir = 1;
270
271 freqs.old = calc_speed(longhaul_get_cp
272 freqs.new = speed;
273 freqs.cpu = 0; /* longhaul.c is UP onl
274
275 cpufreq_notify_transition(&freqs, CPUF
276
277 dprintk ("Setting to FSB:%dMHz Mult:%d
278 fsb, mult/10, mult%10,
279 retry_loop:
280 preempt_disable();
281 local_irq_save(flags);
282
283 pic2_mask = inb(0xA1);
284 pic1_mask = inb(0x21); /* works on C3
285 outb(0xFF,0xA1); /* Overkill */
286 outb(0xFE,0x21); /* TMR0 only *
287
288 /* Wait while PCI bus is busy. */
289 if (acpi_regs_addr && (longhaul_flags
290 || ((pr != NULL) && pr->flags.bm_c
291 bm_status = inw(acpi_regs_addr
292 bm_status &= 1 << 4;
293 while (bm_status && bm_timeout
294 outw(1 << 4, acpi_regs
295 bm_timeout--;
296 bm_status = inw(acpi_r
297 bm_status &= 1 << 4;
298 }
299 }
300
301 if (longhaul_flags & USE_NORTHBRIDGE)
302 /* Disable AGP and PCI arbiter
303 outb(3, 0x22);
304 } else if ((pr != NULL) && pr->flags.b
305 /* Disable bus master arbitrat
306 acpi_set_register(ACPI_BITREG_
307 }
308 switch (longhaul_version) {
309
310 /*
311 * Longhaul v1. (Samuel[C5A] and Samue
312 * Software controlled multipliers onl
313 */
314 case TYPE_LONGHAUL_V1:
315 do_longhaul1(clock_ratio_index
316 break;
317
318 /*
319 * Longhaul v2 appears in Samuel2 Step
320 *
321 * Longhaul v3 (aka Powersaver). (Ezra
322 * Nehemiah can do FSB scaling too, bu
323 * to work in practice.
324 */
325 case TYPE_LONGHAUL_V2:
326 case TYPE_POWERSAVER:
327 if (longhaul_flags & USE_ACPI_
328 /* Don't allow wakeup
329 acpi_set_register(ACPI
330 do_powersaver(cx->addr
331 } else {
332 do_powersaver(0, clock
333 }
334 break;
335 }
336
337 if (longhaul_flags & USE_NORTHBRIDGE)
338 /* Enable arbiters */
339 outb(0, 0x22);
340 } else if ((pr != NULL) && pr->flags.b
341 /* Enable bus master arbitrati
342 acpi_set_register(ACPI_BITREG_
343 }
344 outb(pic2_mask,0xA1); /* restore mas
345 outb(pic1_mask,0x21);
346
347 local_irq_restore(flags);
348 preempt_enable();
349
350 freqs.new = calc_speed(longhaul_get_cp
351 /* Check if requested frequency is set
352 if (unlikely(freqs.new != speed)) {
353 printk(KERN_INFO PFX "Failed t
354 /* Revision ID = 1 but process
355 * equal to 0. Jumpers at the
356 * multiplier and FSB, but wil
357 * MSR nor enable voltage scal
358 if (!revid_errata) {
359 printk(KERN_INFO PFX "
360
361 revid_errata = 1;
362 msleep(200);
363 goto retry_loop;
364 }
365 /* Why ACPI C3 sometimes doesn
366 * But it does happen. Process
367 * but it doesn't change frequ
368 * bits in northbridge registe
369 if (longhaul_flags & USE_ACPI_
370 printk(KERN_INFO PFX "
371 longhaul_flags &= ~USE
372 if (revid_errata) {
373 printk(KERN_IN
374
375 revid_errata =
376 }
377 msleep(200);
378 goto retry_loop;
379 }
380 /* This shouldn't happen. Long
381 * working on processors witho
382 * RevID = 1. RevID errata wil
383 * to be 100% sure. */
384 if (longhaul_version == TYPE_L
385 printk(KERN_INFO PFX "
386 longhaul_version = TYP
387 msleep(200);
388 goto retry_loop;
389 }
390 }
391 /* Report true CPU frequency */
392 cpufreq_notify_transition(&freqs, CPUF
393
394 if (!bm_timeout)
395 printk(KERN_INFO PFX "Warning:
396 }
397
398 /*
399 * Centaur decided to make life a little more
400 * Only longhaul v1 is allowed to read EBLCR B
401 * Samuel2 and above have to try and guess wha
402 * We do this by assuming we booted at maximum
403 * between that value multiplied by possible F
404 * was calculated at boot time. Really ugly, b
405 */
406
407 #define ROUNDING 0xf
408
409 static int guess_fsb(int mult)
410 {
411 int speed = cpu_khz / 1000;
412 int i;
413 int speeds[] = { 666, 1000, 1333, 2000
414 int f_max, f_min;
415
416 for (i = 0; i < 4; i++) {
417 f_max = ((speeds[i] * mult) +
418 f_max += (ROUNDING / 2);
419 f_min = f_max - ROUNDING;
420 if ((speed <= f_max) && (speed
421 return speeds[i] / 10;
422 }
423 return 0;
424 }
425
426
427 static int __init longhaul_get_ranges(void)
428 {
429 unsigned int i, j, k = 0;
430 unsigned int ratio;
431 int mult;
432
433 /* Get current frequency */
434 mult = longhaul_get_cpu_mult();
435 if (mult == -1) {
436 printk(KERN_INFO PFX "Invalid
437 return -EINVAL;
438 }
439 fsb = guess_fsb(mult);
440 if (fsb == 0) {
441 printk(KERN_INFO PFX "Invalid
442 return -EINVAL;
443 }
444 /* Get max multiplier - as we always d
445 * Longhaul MSR is usefull only when v
446 * C3 is booting at max anyway. */
447 maxmult = mult;
448 /* Get min multiplier */
449 switch (cpu_model) {
450 case CPU_NEHEMIAH:
451 minmult = 50;
452 break;
453 case CPU_NEHEMIAH_C:
454 minmult = 40;
455 break;
456 default:
457 minmult = 30;
458 break;
459 }
460
461 dprintk ("MinMult:%d.%dx MaxMult:%d.%d
462 minmult/10, minmult%10, maxmu
463
464 highest_speed = calc_speed(maxmult);
465 lowest_speed = calc_speed(minmult);
466 dprintk ("FSB:%dMHz Lowest speed: %s
467 print_speed(lowest_speed/1000
468 print_speed(highest_speed/100
469
470 if (lowest_speed == highest_speed) {
471 printk (KERN_INFO PFX "highest
472 return -EINVAL;
473 }
474 if (lowest_speed > highest_speed) {
475 printk (KERN_INFO PFX "nonsens
476 lowest_speed, highest_
477 return -EINVAL;
478 }
479
480 longhaul_table = kmalloc((numscales +
481 if(!longhaul_table)
482 return -ENOMEM;
483
484 for (j = 0; j < numscales; j++) {
485 ratio = clock_ratio[j];
486 if (ratio == -1)
487 continue;
488 if (ratio > maxmult || ratio <
489 continue;
490 longhaul_table[k].frequency =
491 longhaul_table[k].index = j;
492 k++;
493 }
494 if (k <= 1) {
495 kfree(longhaul_table);
496 return -ENODEV;
497 }
498 /* Sort */
499 for (j = 0; j < k - 1; j++) {
500 unsigned int min_f, min_i;
501 min_f = longhaul_table[j].freq
502 min_i = j;
503 for (i = j + 1; i < k; i++) {
504 if (longhaul_table[i].
505 min_f = longha
506 min_i = i;
507 }
508 }
509 if (min_i != j) {
510 unsigned int temp;
511 temp = longhaul_table[
512 longhaul_table[j].freq
513 longhaul_table[min_i].
514 temp = longhaul_table[
515 longhaul_table[j].inde
516 longhaul_table[min_i].
517 }
518 }
519
520 longhaul_table[k].frequency = CPUFREQ_
521
522 /* Find index we are running on */
523 for (j = 0; j < k; j++) {
524 if (clock_ratio[longhaul_table
525 longhaul_index = j;
526 break;
527 }
528 }
529 return 0;
530 }
531
532
533 static void __init longhaul_setup_voltagescali
534 {
535 union msr_longhaul longhaul;
536 struct mV_pos minvid, maxvid, vid;
537 unsigned int j, speed, pos, kHz_step,
538 int min_vid_speed;
539
540 rdmsrl(MSR_VIA_LONGHAUL, longhaul.val)
541 if (!(longhaul.bits.RevisionID & 1)) {
542 printk(KERN_INFO PFX "Voltage
543 return;
544 }
545
546 if (!longhaul.bits.VRMRev) {
547 printk(KERN_INFO PFX "VRM 8.5\
548 vrm_mV_table = &vrm85_mV[0];
549 mV_vrm_table = &mV_vrm85[0];
550 } else {
551 printk(KERN_INFO PFX "Mobile V
552 if (cpu_model < CPU_NEHEMIAH)
553 return;
554 vrm_mV_table = &mobilevrm_mV[0
555 mV_vrm_table = &mV_mobilevrm[0
556 }
557
558 minvid = vrm_mV_table[longhaul.bits.Mi
559 maxvid = vrm_mV_table[longhaul.bits.Ma
560
561 if (minvid.mV == 0 || maxvid.mV == 0 |
562 printk (KERN_INFO PFX "Bogus v
563 "Volta
564 minvid
565 return;
566 }
567
568 if (minvid.mV == maxvid.mV) {
569 printk (KERN_INFO PFX "Claims
570 "both %d.%03d.
571 maxvid.mV/1000
572 return;
573 }
574
575 /* How many voltage steps */
576 numvscales = maxvid.pos - minvid.pos +
577 printk(KERN_INFO PFX
578 "Max VID=%d.%03d "
579 "Min VID=%d.%03d, "
580 "%d possible voltage scales\n"
581 maxvid.mV/1000, maxvid.mV%1000
582 minvid.mV/1000, minvid.mV%1000
583 numvscales);
584
585 /* Calculate max frequency at min volt
586 j = longhaul.bits.MinMHzBR;
587 if (longhaul.bits.MinMHzBR4)
588 j += 16;
589 min_vid_speed = eblcr_table[j];
590 if (min_vid_speed == -1)
591 return;
592 switch (longhaul.bits.MinMHzFSB) {
593 case 0:
594 min_vid_speed *= 13333;
595 break;
596 case 1:
597 min_vid_speed *= 10000;
598 break;
599 case 3:
600 min_vid_speed *= 6666;
601 break;
602 default:
603 return;
604 break;
605 }
606 if (min_vid_speed >= highest_speed)
607 return;
608 /* Calculate kHz for one voltage step
609 kHz_step = (highest_speed - min_vid_sp
610
611 j = 0;
612 while (longhaul_table[j].frequency !=
613 speed = longhaul_table[j].freq
614 if (speed > min_vid_speed)
615 pos = (speed - min_vid
616 else
617 pos = minvid.pos;
618 longhaul_table[j].index |= mV_
619 vid = vrm_mV_table[mV_vrm_tabl
620 printk(KERN_INFO PFX "f: %d kH
621 j++;
622 }
623
624 can_scale_voltage = 1;
625 printk(KERN_INFO PFX "Voltage scaling
626 }
627
628
629 static int longhaul_verify(struct cpufreq_poli
630 {
631 return cpufreq_frequency_table_verify(
632 }
633
634
635 static int longhaul_target(struct cpufreq_poli
636 unsigned int targe
637 {
638 unsigned int table_index = 0;
639 unsigned int i;
640 unsigned int dir = 0;
641 u8 vid, current_vid;
642
643 if (cpufreq_frequency_table_target(pol
644 return -EINVAL;
645
646 /* Don't set same frequency again */
647 if (longhaul_index == table_index)
648 return 0;
649
650 if (!can_scale_voltage)
651 longhaul_setstate(table_index)
652 else {
653 /* On test system voltage tran
654 * step up or down were turnin
655 * "ondemand" and "userspace"
656 * this in hardware, C3 is old
657 * in software. */
658 i = longhaul_index;
659 current_vid = (longhaul_table[
660 if (table_index > longhaul_ind
661 dir = 1;
662 while (i != table_index) {
663 vid = (longhaul_table[
664 if (vid != current_vid
665 longhaul_setst
666 current_vid =
667 msleep(200);
668 }
669 if (dir)
670 i++;
671 else
672 i--;
673 }
674 longhaul_setstate(table_index)
675 }
676 longhaul_index = table_index;
677 return 0;
678 }
679
680
681 static unsigned int longhaul_get(unsigned int
682 {
683 if (cpu)
684 return 0;
685 return calc_speed(longhaul_get_cpu_mul
686 }
687
688 static acpi_status longhaul_walk_callback(acpi
689 u32
690 void
691 {
692 struct acpi_device *d;
693
694 if ( acpi_bus_get_device(obj_handle, &
695 return 0;
696 }
697 *return_value = acpi_driver_data(d);
698 return 1;
699 }
700
701 /* VIA don't support PM2 reg, but have somethi
702 static int enable_arbiter_disable(void)
703 {
704 struct pci_dev *dev;
705 int status = 1;
706 int reg;
707 u8 pci_cmd;
708
709 /* Find PLE133 host bridge */
710 reg = 0x78;
711 dev = pci_get_device(PCI_VENDOR_ID_VIA
712 NULL);
713 /* Find PM133/VT8605 host bridge */
714 if (dev == NULL)
715 dev = pci_get_device(PCI_VENDO
716 PCI_DEVIC
717 /* Find CLE266 host bridge */
718 if (dev == NULL) {
719 reg = 0x76;
720 dev = pci_get_device(PCI_VENDO
721 PCI_DEVIC
722 /* Find CN400 V-Link host brid
723 if (dev == NULL)
724 dev = pci_get_device(P
725 }
726 if (dev != NULL) {
727 /* Enable access to port 0x22
728 pci_read_config_byte(dev, reg,
729 if (!(pci_cmd & 1<<7)) {
730 pci_cmd |= 1<<7;
731 pci_write_config_byte(
732 pci_read_config_byte(d
733 if (!(pci_cmd & 1<<7))
734 printk(KERN_ER
735 "Can't
736 status = 0;
737 }
738 }
739 pci_dev_put(dev);
740 return status;
741 }
742 return 0;
743 }
744
745 static int longhaul_setup_southbridge(void)
746 {
747 struct pci_dev *dev;
748 u8 pci_cmd;
749
750 /* Find VT8235 southbridge */
751 dev = pci_get_device(PCI_VENDOR_ID_VIA
752 if (dev == NULL)
753 /* Find VT8237 southbridge */
754 dev = pci_get_device(PCI_VENDO
755 PCI_DEVIC
756 if (dev != NULL) {
757 /* Set transition time to max
758 pci_read_config_byte(dev, 0xec
759 pci_cmd &= ~(1 << 2);
760 pci_write_config_byte(dev, 0xe
761 pci_read_config_byte(dev, 0xe4
762 pci_cmd &= ~(1 << 7);
763 pci_write_config_byte(dev, 0xe
764 pci_read_config_byte(dev, 0xe5
765 pci_cmd |= 1 << 7;
766 pci_write_config_byte(dev, 0xe
767 /* Get address of ACPI registe
768 pci_read_config_byte(dev, 0x81
769 if (pci_cmd & 1 << 7) {
770 pci_read_config_dword(
771 acpi_regs_addr &= 0xff
772 printk(KERN_INFO PFX "
773 }
774
775 pci_dev_put(dev);
776 return 1;
777 }
778 return 0;
779 }
780
781 static int __init longhaul_cpu_init(struct cpu
782 {
783 struct cpuinfo_x86 *c = &cpu_data(0);
784 char *cpuname=NULL;
785 int ret;
786 u32 lo, hi;
787
788 /* Check what we have on this motherbo
789 switch (c->x86_model) {
790 case 6:
791 cpu_model = CPU_SAMUEL;
792 cpuname = "C3 'Samuel' [C5A]";
793 longhaul_version = TYPE_LONGHA
794 memcpy (clock_ratio, samuel1_c
795 memcpy (eblcr_table, samuel1_e
796 break;
797
798 case 7:
799 switch (c->x86_mask) {
800 case 0:
801 longhaul_version = TYP
802 cpu_model = CPU_SAMUEL
803 cpuname = "C3 'Samuel
804 /* Note, this is not a
805 * Samuel1 ratios. */
806 memcpy(clock_ratio, sa
807 sizeof(samuel1
808 memcpy(eblcr_table, sa
809 sizeof(samuel2
810 break;
811 case 1 ... 15:
812 longhaul_version = TYP
813 if (c->x86_mask < 8) {
814 cpu_model = CP
815 cpuname = "C3
816 } else {
817 cpu_model = CP
818 cpuname = "C3
819 }
820 memcpy(clock_ratio, ez
821 sizeof(ezra_cl
822 memcpy(eblcr_table, ez
823 sizeof(ezra_eb
824 break;
825 }
826 break;
827
828 case 8:
829 cpu_model = CPU_EZRA_T;
830 cpuname = "C3 'Ezra-T' [C5M]";
831 longhaul_version = TYPE_POWERS
832 numscales=32;
833 memcpy (clock_ratio, ezrat_clo
834 memcpy (eblcr_table, ezrat_ebl
835 break;
836
837 case 9:
838 longhaul_version = TYPE_POWERS
839 numscales = 32;
840 memcpy(clock_ratio,
841 nehemiah_clock_ratio,
842 sizeof(nehemiah_clock_r
843 memcpy(eblcr_table, nehemiah_e
844 switch (c->x86_mask) {
845 case 0 ... 1:
846 cpu_model = CPU_NEHEMI
847 cpuname = "C3 'Nehemia
848 break;
849 case 2 ... 4:
850 cpu_model = CPU_NEHEMI
851 cpuname = "C3 'Nehemia
852 break;
853 case 5 ... 15:
854 cpu_model = CPU_NEHEMI
855 cpuname = "C3 'Nehemia
856 break;
857 }
858 break;
859
860 default:
861 cpuname = "Unknown";
862 break;
863 }
864 /* Check Longhaul ver. 2 */
865 if (longhaul_version == TYPE_LONGHAUL_
866 rdmsr(MSR_VIA_LONGHAUL, lo, hi
867 if (lo == 0 && hi == 0)
868 /* Looks like MSR isn'
869 longhaul_version = TYP
870 }
871
872 printk (KERN_INFO PFX "VIA %s CPU dete
873 switch (longhaul_version) {
874 case TYPE_LONGHAUL_V1:
875 case TYPE_LONGHAUL_V2:
876 printk ("Longhaul v%d supporte
877 break;
878 case TYPE_POWERSAVER:
879 printk ("Powersaver supported.
880 break;
881 };
882
883 /* Doesn't hurt */
884 longhaul_setup_southbridge();
885
886 /* Find ACPI data for processor */
887 acpi_walk_namespace(ACPI_TYPE_PROCESSO
888 ACPI_UINT32_MA
889 NULL, (void *)
890
891 /* Check ACPI support for C3 state */
892 if (pr != NULL && longhaul_version ==
893 cx = &pr->power.states[ACPI_ST
894 if (cx->address > 0 && cx->lat
895 longhaul_flags |= USE_
896 }
897 /* Disable if it isn't working */
898 if (disable_acpi_c3)
899 longhaul_flags &= ~USE_ACPI_C3
900 /* Check if northbridge is friendly */
901 if (enable_arbiter_disable())
902 longhaul_flags |= USE_NORTHBRI
903
904 /* Check ACPI support for bus master a
905 if (!(longhaul_flags & USE_ACPI_C3
906 || longhaul_flags & USE_NORTHBRID
907 && ((pr == NULL) || !(pr->flags.bm
908 printk(KERN_ERR PFX
909 "No ACPI support. Unsu
910 return -ENODEV;
911 }
912
913 if (longhaul_flags & USE_NORTHBRIDGE)
914 printk(KERN_INFO PFX "Using no
915 if (longhaul_flags & USE_ACPI_C3)
916 printk(KERN_INFO PFX "Using AC
917
918 ret = longhaul_get_ranges();
919 if (ret != 0)
920 return ret;
921
922 if ((longhaul_version != TYPE_LONGHAUL
923 longhaul_setup_voltagescaling(
924
925 policy->cpuinfo.transition_latency = 2
926 policy->cur = calc_speed(longhaul_get_
927
928 ret = cpufreq_frequency_table_cpuinfo(
929 if (ret)
930 return ret;
931
932 cpufreq_frequency_table_get_attr(longh
933
934 return 0;
935 }
936
937 static int __devexit longhaul_cpu_exit(struct
938 {
939 cpufreq_frequency_table_put_attr(polic
940 return 0;
941 }
942
943 static struct freq_attr* longhaul_attr[] = {
944 &cpufreq_freq_attr_scaling_available_f
945 NULL,
946 };
947
948 static struct cpufreq_driver longhaul_driver =
949 .verify = longhaul_verify,
950 .target = longhaul_target,
951 .get = longhaul_get,
952 .init = longhaul_cpu_init,
953 .exit = __devexit_p(longhaul_cpu_exi
954 .name = "longhaul",
955 .owner = THIS_MODULE,
956 .attr = longhaul_attr,
957 };
958
959
960 static int __init longhaul_init(void)
961 {
962 struct cpuinfo_x86 *c = &cpu_data(0);
963
964 if (c->x86_vendor != X86_VENDOR_CENTAU
965 return -ENODEV;
966
967 #ifdef CONFIG_SMP
968 if (num_online_cpus() > 1) {
969 printk(KERN_ERR PFX "More than
970 return -ENODEV;
971 }
972 #endif
973 #ifdef CONFIG_X86_IO_APIC
974 if (cpu_has_apic) {
975 printk(KERN_ERR PFX "APIC dete
976 return -ENODEV;
977 }
978 #endif
979 switch (c->x86_model) {
980 case 6 ... 9:
981 return cpufreq_register_driver
982 case 10:
983 printk(KERN_ERR PFX "Use acpi-
984 default:
985 ;;
986 }
987
988 return -ENODEV;
989 }
990
991
992 static void __exit longhaul_exit(void)
993 {
994 int i;
995
996 for (i=0; i < numscales; i++) {
997 if (clock_ratio[i] == maxmult)
998 longhaul_setstate(i);
999 break;
1000 }
1001 }
1002
1003 cpufreq_unregister_driver(&longhaul_d
1004 kfree(longhaul_table);
1005 }
1006
1007 /* Even if BIOS is exporting ACPI C3 state, a
1008 * with success when CPU is idle, this state
1009 * trigger frequency transition in some cases
1010 module_param (disable_acpi_c3, int, 0644);
1011 MODULE_PARM_DESC(disable_acpi_c3, "Don't use
1012 /* Change CPU voltage with frequency. Very us
1013 * power, but most VIA C3 processors aren't s
1014 module_param (scale_voltage, int, 0644);
1015 MODULE_PARM_DESC(scale_voltage, "Scale voltag
1016 /* Force revision key to 0 for processors whi
1017 * support voltage scaling, but are introduci
1018 * such. */
1019 module_param(revid_errata, int, 0644);
1020 MODULE_PARM_DESC(revid_errata, "Ignore CPU Re
1021
1022 MODULE_AUTHOR ("Dave Jones <davej@codemonkey.
1023 MODULE_DESCRIPTION ("Longhaul driver for VIA
1024 MODULE_LICENSE ("GPL");
1025
1026 late_initcall(longhaul_init);
1027 module_exit(longhaul_exit);
1028
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