Parallel Computing: Lecture 2

Learning objectives

After this class, you should be able to:

1. Describe the following: binary tree network topology, bisection width, cache coherence problem, centralized multiprocessor, diameter, directory based cache coherence, distributed multiprocessor, fat tree, Flynn's taxonomy, hypercube, mesh, MIMD, multicomputer, NUMA, processor array, ring, SIMD, SISD, SMP, snooping based cache coherence, torus network topology, vector computer, write invalidate protocol.
2. Given a network topology, give expressions for the diameter, bisection width, and edges to node ratio for that network as functions of the number of processors.
3. Given a network topology and the number of processors, draw a figure to show that topology.
4. Given the number of operations, number of processors, and time per operation on a processor array, compute the performance (as in examples 2.1 and 2.2).
5. Given a sequence of read and write operations on an SMP, draw diagrams to show the states of the caches and memory using the write invalidate protocol for cache coherence using snooping.
6. Given a sequence of read and write operations on a NUMA machine, draw diagrams to show the states of the caches, directory, and memory, using a directory-based protocol for cache coherence, as illustrated in figure 2.16.

Reading assignment

1. Chapter 2, except sections: 2.2.5, 2.2.6, 2.2.8, 2.5.1, 2.5.2, 2.6.3. Slides on Parallel Architectures. Handout on Data Parallel Processing.
2. None.

Exercises and review questions

• Questions on current lecture's material
  1. Exercise 2.3.
  2. Exercise 2.7.
  3. Exercise 2.14 (only for sizes 1, 10, 20, 30, 40, and 50).
  4. Exercise 2.19.

• Questions on next lecture's material
  1. None.