Dr. David Whalley received his Ph.D. in Computer Science at the University of Virginia in 1990. He joined FSU as an assistant professor of Computer Science in 1990, becoming an associate professor in 1995, and a full professor in 2000. He has directed seven Ph.D. dissertations with another two in progress and is the author or coauthor of over 80 papers. He has served on numerous program committees for workshops and conferences and is currently on the editorial board of the Journal of Embedded Computing. He is the E.P. Miles Professor of Computer Science.
Research
Dr. Whalley\'s research interests include compilers, computer architecture, embedded systems, and performance evaluation. Over the years he has developed compiler optimizations, techniques for predicting the worst-case execution time of real-time tasks, fast methods for obtaining performance measures, and a number of compilation tools to ease the process of developing and enhancing a compiler. He recently has investigated both architectural and compilation issues involving embedded systems.
Selected Publications
- “Automatic Detection and Exploitation of Branch Constraints for Timing Analysis” by C. Healy and D. Whalley, in IEEE Transactions on Software Engineering, August 2002, pages 763-781.
- “Efficient and Effective Branch Reordering Using Profile Data” by M. Yang, G. Uh, and D. Whalley, in ACM Transactions on Programming Languages and Systems, vol 24, no 6, November 2002, pages 667-697.
- \"Fast and Efficient Searches for Effective Optimization Phase Sequences\" by P. Kulkarni, S. Hines, D. Whalley, J. Hiser, J. Davidson, D. Jones, in ACM Transactions on Architecture and Code Optimization, June 2005, pages 165-198.
- \"Improving Program Efficiency by Packing Instructions into Registers\" by S. Hines, J. Green, G. Tyson, D. Whalley in the Proceedings of the IEEE/ACM International Symposium on Computer Architecture, June 2005, pages 260-271.
